Implement High-Performance Physical Prototypes 

The Certify software enables implementation and partitioning for ASIC designers who use Xilinx Virtex-7 and Altera Stratix-V based physical prototypes to verify their designs. The Certify software provides a way to convert and partition of large ASIC designs onto multi-FPGA prototyping boards.

Prototyping with the Synopsys HAPS Series only? Learn how HAPS ProtoCompiler helps improve productivity and shorten time to first prototype. 

Key Features
  • Supports high-capacity Xilinx Virtex-7 and Altera Stratix-V based FPGA devices popular for physical prototyping
  • Create custom board file descriptions with Verilog HDL syntax
  • Automatic mapping of ASIC style RTL source code and DesignWare® IP to multiple FPGAs
  • Allows automated and/or manual partitioning
  • Swarm Intelligence Partition Engine (SWIPE) finds more feasible partition solutions
  • Impact analysis interface provides immediate FPGA resource consumption feedback during interactive partitioning
  • Supports Synopsys Design Constraints for timing management
  • Includes industry standard Synplify® Premier synthesis engine
  • Includes Identify® RTL Debugger for simulator-like visibility into FPGA hardware
  • Includes library of HAPS®-70 series motherboard and daughter board descriptions for immediate planning and implementation
  • Offers High-Speed Time Domain Multiplexing (HSTDM) I/O sharing to increase FPGA interconnection bandwidth

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Figure 1: Flow based graphical interface guides the user
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Design Implementation
In order to prototype an ASIC design using FPGAs certain design elements must be converted to structures that are recognizable by FPGA implementation tools. These elements, such as ASIC gate-level components or gated-clock tree structures, can be very difficult and time-consuming to edit manually. The Certify software automatically recognizes and converts these ASIC-specific constructs into equivalent FPGA structures.

The Certify tool's automated mode partitions basic designs quickly with minimal user intervention by employing an intuitive, flow-driven graphical user interface (GUI). For more complex designs, this flow-driven GUI will guide the user through the partitioning process and provide utilities such as I/O pin multiplexing designed to reduce the number of I/O pins between FPGA partitions. Users can create functional partition solutions quickly and use the Certify tool's advanced features to optimize these solutions.

The Certify tool supports system timing constraints, defined in industry standard Synopsys Design Constraint (SDC) format - ensuring that the overall ASIC timing is matched by the multi-FPGA implementation. The Certify software can also provide a timing report outlining the approximate performance of the prototype prior to programming the hardware. With the Certify software, users are assured that the timing constraints for the ASIC are achieved by the equivalent multi-FPGA prototyping implementation. Additionally the tool's new High-speed Time Domain Multiplexing (HSTDM) technology offers a way to increase FPGA interconnect bandwidth on HAPS boards to significantly boost system performance.

Figure 2: Certify is the key to multi-FPGA-based prototyping implementation

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