Certify® Multi-FPGA Implementation and Partitioning Software 

Part of the Confirma™ ASIC/ASSP/SoC Rapid Prototyping Platform 

Verification is the most time consuming task in ASIC design today. The Certify ASIC RTL prototyping software from Synopsys helps to accelerate the verification phase by allowing you to build multi-FPGA based prototypes of ASIC designs in an easy, intuitive fashion, with no modifications to the original design. Certify is being used successfully at hundreds of sites and is a user-friendly tool that works directly from your RTL code. Certify is tightly integrated with the other hardware and software tools that make up the Confirma rapid prototyping platform.

Certify Highlights
  • Easy-to-use graphical user interface flow guide
  • Automatic and manual partitioning
  • Automates tasks such as gated-clock conversion, I/O pin multiplexing and signal-to-trace assignments
  • Uses Synopsys design constraints to manage timing
  • Tightly integrated with Confirma flow hardware
  • Supports multi-core parallel processing for faster runtimes
  • Supports most leading FPGA devices
  • Industry standard Synplify Premier synthesis engine included

Rapid RTL Prototyping with Multiple FPGAs
The Certify tool dramatically reduces the time required to produce a multi-FPGA prototype. Multi-chip timing analysis and time budgeting are built into the Certify tool, enabling simultaneous partitioning and optimization of a design spanning multiple FPGAs. Only the Certify product has the capacity to accept multi-million gate ASIC RTL source and synthesize it directly into multiple FPGAs. It does this without requiring changes to the RTL source code or having to break up the design into many small blocks to be able to run synthesis. Multicore parallel processing allows easy execution of multiple synthesis jobs, significantly speeding up the mapping and optimization processes.

Figure 1: Certify® User Interface

How the Certify Tool Eliminates Iterations
Certify is a single tool that allows you to partition, synthesize and enable debug. It allows you to determine the actual performance of a design before it is built, eliminating costly iterations of the prototype. Certify's model-based area estimation feature and Quick Partitioning Technology (QPT) give you the ability to quickly partition and estimate your area utilization. For your debug needs, the Certify tool inserts debug logic into the design without modifying the original ASIC RTL and provides multiple ways to observe signals in real time. Automatic timing analysis across multiple FPGAS enables a prototype to be built that runs at or near real-time speeds. You can quickly obtain timing estimates and therefore try different combinations, including different target hardware, before building the actual prototype. The Certify product shortens the prototype development cycle, improves prototype performance, and enables faster time to market by enabling faster ASIC verification.

Flexibility to Fit into Your Flow
Certify easily integrates into your current process and you can use the flow-based GUI to learn how to use the tool. All graphical commands are also recorded as Tcl commands to allow you to easily script your design flow. Synopsys Design Constraints (SDC) are supported to allow you to use your existing ASIC constraints to drive the partitioning process and to ensure that your prototype system performance is the same as that of your target design. Certify supports both RTL and EDIF or netist level designs, allowing you to partition new projects that may only be in RTL and existing designs that may already be at the EDIF or netlist-level of abstraction.

Part of the Confirma™ ASIC/ ASSP/SoC Rapid Prototyping Platform
The Confirma platform is a comprehensive at-speed ASIC/ASSP verification flow that dramatically accelerates the functional verification of FPGAs and ASICs. In addition to the Certify software, the Confirma platform includes the Synplify® Premier single- FPGA implementation tool, the Identify® Pro full-visibility debugging tool, the CHIPit Automated Rapid Prototyping Systems and the HAPS™ Highperformance ASIC Prototyping System™.

Platform and FPGA Device Support
Certify supports Windows and Linux 32-bit and 64-bit operating systems. Ceritfy also supports most common FPGA devices including Stratix III and Stratix IV from Altera and Virtex-4 and Virtex-5 from Xilinx. New devices are supported as they become available.

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