|Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures|
LPDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper discusses why designers are selecting LPDDR4, how to handle 2-die and 4-die packages with multi-channel connections, the advantages of sharing channels through system-on-chip (SoC) partitioning, and how to optimize channels for the lowest power consumption.
Marc Greenberg, Director of Product Marketing for DDR IP, Synopsys
|Addressing Three Critical Challenges of USB Type-C Implementation|
As designers create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of partitioning challenges. The SoC and system design must be partitioned to support the specification’s requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute on the processor, internal microcontroller, microcontroller in a power management IC, and/or on an external dedicated USB Type-C chip. This white paper describes key challenges and suggests solutions for designers of USB Type-C products and SoCs with native USB Type-C support.
Morten Christiansen, Technical Marketing Manager, USB, Synopsys
|Anatomy of the HDMI IP Certification Flow|
HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).
Dr. Antonio J. Salazar E., ASIC Digital Design Engineer, Synopsys; Hugo Faria, Embedded Software and Protocol Validation Engineer, Synopsys; Quintin D. Anderson, Co-Founder and COO, Granite River Labs
|Virtualizing Cloud Computing With Optimized IP for NFV SoCs|
The growth in internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications. This paper discusses how using the right IP accelerates the implementation of SoCs used in NFV systems.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
|PCI Express 4.0 Controller Design and Integration Challenges|
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers.
Scott Knowlton, Sr. Product Marketing Manager, DesignWare Controller IP for PCI Express; Richard Solomon, Sr. Technical Marketing Manager, DesignWare Controller IP for PCI Express
|Ethernet in the Connected World|
This white paper outlines the latest networking trends across some of the key market sectors including automotive, the connected home and data centers, and explains how Ethernet is relevant to each. It also explains how Synopsys responds to its customers’ needs to develop and offer configurable semiconductor IP that enables system-on-chip (SoC) design teams to quickly and reliably implement Ethernet-based digital controllers and physical layers.
John A. Swanson, Ethernet Product Line Manager, Synopsys
|Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market|
This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality IP alone is not enough to accelerate time-to-market with today’s SoC complexity. The paper will also discuss issues around driver software development for the IP. Finally, it will review the five major development steps in any SoC design and how third-party IP providers should be expected to help accelerate each of these steps.
Dr. Johannes Stahl, Director of Prototyping Product Marketing, Synopsys, Inc.
|Meeting the USB IP Requirements of SoC Designs from 180-nm to 14/16-nm FinFET|
USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper addresses the five critical challenges facing designers of USB IP who need to keep pace with the process technology changes as well as the USB standard evolution.
Gervais Fong, Sr. USB Product Marketing Manager, Synopsys
|How VXLAN-Based Ethernet IP Solves Cloud Computing Network Bottlenecks|
Network virtualization technologies running over optimized Ethernet IP are enabling cloud computing data centers to expand and support the growing amount of internet traffic. Hyperscale cloud data centers are driving requirements for new network overlay protocols such as Virtual Extensible LAN (VXLAN) running over Ethernet. This whitepaper discusses in detail the benefits of VXLAN and how it can be used to overcome network subnet limits as well as the impact of VXLAN to Ethernet IP implementations. It will also describe how IP supporting VXLAN enables a new class of SoCs optimized for next-generation network virtualization.
Ron DIGiuseppe, Sr. Strategic Marketing Manager, Synopsys
|Reliability, Availability and Serviceability (RAS) for Memory Interfaces|
Smaller process geometries and higher Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) interface speeds are driving demand for new and more robust techniques for preventing, repairing and detecting memory errors. Some of these techniques are enabled by features in the latest DDR4 and DDR3 RDIMM standards, and others can be applied to any DRAM type. Collectively these techniques improve the Reliability, Availability, and Serviceability (RAS) of the computing system that adopts them. This white paper reviews some of the ways that errors can occur in the DDR DRAM memory subsystem and discusses current and future methods of improving RAS in the presence of these errors.
Marc Greenberg, Product Marketing Director, DDR Controllers, Synopsys, Inc.
|USB 3.1: Evolution and Revolution|
USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defined in the USB 3.0 specification.
Morten Christiansen, Technical Marketing Manager, USB IP, Synopsys; Eric Huang, Product Marketing Manager, USB IP, Synopsys
|Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY-IP |
This white paper discusses how a MIPI M-PHY using High-Speed Gear3 operation can provide power-efficient high-speed links for a variety of mobile chip-to-chip communication standards and protocols, such as JEDEC Universal Flash Storage (UFS), USB 3.0 SuperSpeed Inter-chip (SSIC), and PCI-SIG M-PCIe®, each of which are optimized for its particular purpose. The paper then explains how designers can solve signal integrity challenges in implementation, including channel loss, interconnect, and electromagnetic interference (EMI) issues.
Sérgio Silva, Project Director, MIPI M-PHY IP, Synopsys, Inc. ; Hezi Saar, Product Marketing Manager, MIPI IP, Synopsys, Inc.
|How HDMI 2.0 Will Enrich the Multimedia Experience|
With an install base of over 3 billion devices worldwide1, HDMI has become the de facto multimedia interface for all digital home and mobile multimedia devices. To offer consumers the ultimate home theater experience, SoC designers must understand the new features offered by HDMI 2.0, as well as additional features that will drive the adoption of HDMI in industrial, office, and gaming applications.
This white paper describes the HDMI 2.0 specification and compares the new revision of the HDMI specification with the previous versions, HDMI 1.3 and HDMI 1.4. It explains how HDMI 2.0 will almost double the bandwidth from 10.2 Gbps to 18 Gbps to offer 4K video formats at 60 Hz frame rate for an ultra-high definition (ultra-HD) experience on digital TVs. It discusses additional features, such as CEC 2.0, 21:9 frame formats, multi-view video, and HDCP 2.2 for digital rights management. Finally, it will explain HDMI 2.0’s impact on new markets and applications.
Manmeet Walia, Product Marketing Manager, Synopsys Inc.; Luis Laranjeira, R&D Manager, Synopsys Inc.
|Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer|
The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in DesignWare uMCTL and uMCTL2 DDR memory controller IP products. This white paper will explain the concept of the read reorder buffer and explain how a read reorder buffer can improve memory bandwidth. It then concludes with experimental results showing how DRAM controllers with different architectures can achieve vastly different DRAM bus utilizations of 10%, 66%, or 100% from the same input traffic stream, depending on whether the architecture has no RRB, an RRB with external scheduling, or an RRB with content-addressable memory (CAM)-based scheduling.
Marc Greenberg, Product Marketing Director, DDR Controllers, Synopsys
|Technical Considerations for Implementing USB 3.0 on SoCs|
This paper highlights the specific features and enhancements in the USB 3.0 protocol. These
enhancements come with technical complexities, and this paper outlines complexities and the resulting
design challenges. It shows how a USB 3.0 core's reconfigurability can broaden a design's potential
applications and reuse. Finally, it talks about USB 3.0 selection and implementation considerations, from
architecture, prototyping, and software, to testing and certification.
Gervais Fong, Senior Product Marketing Manager, Synopsys, Inc.; Eric Huang, Senior Product Marketing Manager, Synopsys, Inc.
|Shrinking SoC Design Cycles Using DesignWare Intellectual Property|
In this case study, it was discussed how DesignWare IP was leveraged, including USB 2.0 host, USB 2.0 Hi-Speed OTG, Ethernet Controller and SATA, to meet key requirements of IP integration, verification and synthesis to complete a successful design in a short design cycle. The results are highlighted, discussing the issues and the methodology that can be used to achieve the most out of these DesignWare IP solutions, resulting in a reduced SoC design cycle.
Vijay Kumar Mathur, ST Microelectronics; Gaurav Bhatnagar, ST Microelectronics; Rohitaswa Bhattacharya, ST Microelectronics
|Ethernet Quality-of-Service: New IEEE Specifications Driving a New Generation of Network Products|
As designers look to their next-generation network designs, they are faced with a set of new challenges when developing products that incorporate the common Ethernet interface. To maintain Ethernet as a dominate and long-lasting network interface, the latest IEEE updates, which are targeted at improving networking systems' Quality-of-Service, will be critical to meet the demands of the consumer.
Lokesh Kabra, Senior R&D, Manager, Synopsys, Inc.; John A. Swanson, Senior Staff, Marketing Manager, Synopsys, Inc.
|Debugging SuperSpeed USB Software Using Virtual Prototypes|
Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys' DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges.
Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer, Synopsys, Inc.
|Improving I/O Virtualization Performance with PCI Express|
This paper provides an introduction to the general concepts of virtualization and I/O virtualization (IOV). It also discusses how IOV is addressed within the PCI Express sepcification and how to support IOV with an existing PCIe interface. Additional topics include: Single-Root IOV, Function Level Reset, Alternative Routing ID and Address Translation Services.
Scott Knowlton, Sr. Product Marketing Manager, Synopsys, Inc.
|SuperSpeed Your SoCs with USB 3.0 IP|
This whitepaper provides a comparison between the USB 3.0 and USB 2.0 standards, highlighting the new capabilities and advancements that have been made with this next-generation SuperSpeed USB standard including: performance, cables and connectors, power efficiency, USB model differences, hardware and software functionality, new protocol layers and streaming.
Dr. Robert Lefferts, R&D Director, Synopsys, Inc.; Subramaniam Aravindhan, R&D Manager, Synopsys, Inc.
|Show Me the Next-Generation HDMI|
Explore the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. In addition, this paper provides a tutorial on the new capabilities of HDMI 1.4 and its role in providing a richer, more straightforward user experience. Example case studies are also presented to illustrate how the HDMI Ethernet and Audio Return Channel (HEAC) feature simplifies cabling requirements.
Manmeet Walia, Product Marketing Manager, Synopsys, Inc.
|DesignWare SATA AHCI Host Controller - Understanding Multi-Port Configuration and Performance|
This whitepaper describes how to configure and connect the DesignWare® SATA AHCI IP core to the DesignWare SATA PHY in a multi-port AHB-based configuration. It provides an analysis of the expected throughput on each port based on assumed system parameters. The intent of this paper is to enable users to take this example and insert actual system parameters to come up with a performance estimate.
Bjorn Widerstrom, Corporate Applications Engineer, Synopsys, Inc.
|Embedded DDR Interfaces: Ten Tips to Success for Your SoC|
Emerging from a host of competing technologies, DDR2 and DDR3 SDRAM ("DDR") have become the dominant off-chip memory storage solution for SoC designs. Unfortunately, many SoC designers are unfamiliar with the realities of the DRAM standards, typical DRAM applications and the DRAM market. This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain.
Graham Allan, Sr. Product Marketing Manager, Synopsys, Inc.
|Enabling Portable, Lower Power HDMI-Based Designs with Interface IP|
By using IP, SoC designers can easily incorporate an HDMI interface in leading edge process technologies such as 90 nanometer (nm), 65 nm and 40 nm processes. This eliminates the need for a separate IC, delivering significant power and cost savings. This paper provides an overview of HDMI standard , how it’s different from other digital video connections and the advantage of incorporating it into your SoC.
Luis Laranjeira, Sr. R&D Manager, Synopsys, Inc.