|Virtualizing Cloud Computing With Optimized IP for NFV SoCs|
The growth in internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications. This paper discusses how using the right IP accelerates the implementation of SoCs used in NFV systems.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
|Addressing IP Integration & Software Development Challenges to Accelerate SoC Time-to-Market|
This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality IP alone is not enough to accelerate time-to-market with today’s SoC complexity. The paper will also discuss issues around driver software development for the IP. Finally, it will review the five major development steps in any SoC design and how third-party IP providers should be expected to help accelerate each of these steps.
Dr. Johannes Stahl, Director of Prototyping Product Marketing, Synopsys, Inc.
|Mixed-Signal IP Design Challenges in 28-nm Process and Beyond|
This whitepaper discusses how specific design challenges at 28-nm impacts power consumption, cores supply voltages, restrictive design rules, and yield. The paper also focuses on unique design techniques and verification methodologies which help ensure robust and manufacturable IP.
Brent Beacham, R&D Manager, Synopsys, Inc.; Paul Hua, R&D Manager, Synopsys, Inc.; Cameron Lacy, R&D Manager, Synopsys, Inc.; Michael Lynch, R&D Manager, Synopsys, Inc.; Dino Toffolon, R&D Director, Synopsys, Inc.
|A Survival Guide for Selecting High-Quality IP |
This paper will explore three important determinants of IP quality: (1) Functional Correctness – extensive configurability of digital IP for standards interfaces and how an IP vendor verifies across a very large number of configurations. (2) Interoperability –probably the single most important criteria for IP and mistakenly equated with compliance, which is required but not sufficient on its own. (3) Ease of Integration –IP that is difficult to integrate will lead to schedule risk and increased cost of the SoC design.
Ed Bard, Sr. Director, Product Marketing, Synopsys, Inc.;
Ralph Morgan, Vice-President, Engineering, Synopsys, Inc.
|The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator |
While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
David Chiapinni, Asic Project Manager, Matrox;
Massimo Vanzi, CEO, Accent;
Navraj Nandra, Director Product Marketing, Mixed-Signal IP, Synopsys, Inc.
|Life Begins at 65 – Unless You Are Mixed-Signal?|
The old school of analog designers, exemplified by pioneer Bob Pease, is becoming an extinct species. But the demand for analog/mixed-signal IP blocks has never been greater, especially at 65 nm and below. Can this demand be met by using externally designed 3rd party analog/mixed-signal IP? Or, is the implementation of revolutionary changes to traditional work flows and analog design processes a suitable option? This paper will answer these questions and more.
Navraj S. Nandra, Director of Product Marketing, Synopsys, Inc.;
Reimund Wittmann, NOKIA Research Center, Bochum, Germany;
Massimo Vanzi, Accent, Vimercate, Milan, Italy
|Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies|
The physical layer is responsible for the transmission of the raw bit stream over the physical transport medium and is the lowest layer within the OSI network model. With high-speed interfaces such as the serial protocols USB 2.0, PCI Express®, SATA, and DDR2, the PHY provides the bridge between the digital and modulated parts of the interface. The trend is to integrate these mixed-signal interfaces into SoC that are manufactured in digital logic deep sub-micron technologies with channel lengths of 65 nm and 45 nm.
Navraj S. Nandra, Director of Marketing Mixed-Signal IP, Synopsys, Inc.
|Reducing AMBA-based SoC Design Time by More Than 50% Using coreAssembler™|
This paper describes how using a knowledge-based IP design and verification flow with coreAssembler can greatly reduce the time needed to assemble, configure, verify and implement a configurable AMBA™ subsystem with IP architected and packaged for use and intelligent assembly and configuration. The focus of this paper will be on the assembly of the subsystem with synthesis, verification and packaging of the subsystem summarized.
John Swanson, Product Marketing Manager, Synopsys, Inc.
|Building a Total Quality Experience into Silicon IP: Delivering DesignWare® Silicon IP into SoC Designs|
Now more than ever, developers of complicated system-on-chip (SoC) designs rely on silicon IP (SIP) both internally developed and from third parties to achieve their time-to-market goals. After nearly 10 years of practice, SIP vendors must deliver a “Total Quality Experience” to buyers. This paper will describe the best way to measure quality which is essentially through direct customer feedback.
Kevin Walsh, Director of Product Marketing, Synopsys, Inc.
|Reverse Disaggregation—How Silicon IP Will Change the Semiconductor Supply Chain|
This paper discusses how reverse disaggregation will drive the creation of a new supply chain for the development of a new generation of products, full featured and assembled at zero cost, and how IP will influence how the new supply chain is created, reversing the disaggregation that has marked the industry until now.
Kevin Walsh, Director of Product Marketing, Synopsys, Inc.