DesignWare IP White Papers 

Leveraging Processor Extensibility to Build an Ultra Low-Power Embedded Subsystem
The ever increasing demand for smaller electronic devices, with more functionality, longer battery life, and shorter time to market has accelerated use of embedded processors and subsystems to offload the host processor from commonly executed tasks. Processor extensions provide a means to extend a general-purpose processor with custom hardware accelerators to optimize the execution of dedicated applications for reduced energy consumption and area, and/or increased performance. This white paper describes how processor extensions can optimize power and performance of a processor when targeting sensor applications, demonstrated using Synopsys’ DesignWare® ARC® Processors and ARC Processor Extensions (APEX) technology.
Jeroen Geuzebroek, Senior R&D Engineer, Synopsys

USB 3.1: Evolution and Revolution
USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defined in the USB 3.0 specification.
Morten Christiansen, Technical Marketing Manager, USB IP, Synopsys; Eric Huang, Product Marketing Manager, USB IP, Synopsys

The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY-IP
This white paper discusses how a MIPI M-PHY using High-Speed Gear3 operation can provide power-efficient high-speed links for a variety of mobile chip-to-chip communication standards and protocols, such as JEDEC Universal Flash Storage (UFS), USB 3.0 SuperSpeed Inter-chip (SSIC), and PCI-SIG M-PCIe®, each of which are optimized for its particular purpose. The paper then explains how designers can solve signal integrity challenges in implementation, including channel loss, interconnect, and electromagnetic interference (EMI) issues.
Sérgio Silva, Project Director, MIPI M-PHY IP, Synopsys, Inc. ; Hezi Saar, Product Marketing Manager, MIPI IP, Synopsys, Inc.

How HDMI 2.0 Will Enrich the Multimedia Experience
With an install base of over 3 billion devices worldwide1, HDMI has become the de facto multimedia interface for all digital home and mobile multimedia devices. To offer consumers the ultimate home theater experience, SoC designers must understand the new features offered by HDMI 2.0, as well as additional features that will drive the adoption of HDMI in industrial, office, and gaming applications. This white paper describes the HDMI 2.0 specification and compares the new revision of the HDMI specification with the previous versions, HDMI 1.3 and HDMI 1.4. It explains how HDMI 2.0 will almost double the bandwidth from 10.2 Gbps to 18 Gbps to offer 4K video formats at 60 Hz frame rate for an ultra-high definition (ultra-HD) experience on digital TVs. It discusses additional features, such as CEC 2.0, 21:9 frame formats, multi-view video, and HDCP 2.2 for digital rights management. Finally, it will explain HDMI 2.0’s impact on new markets and applications.
Manmeet Walia, Product Marketing Manager, Synopsys Inc.; Luis Laranjeira, R&D Manager, Synopsys Inc.

Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer
The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in DesignWare uMCTL and uMCTL2 DDR memory controller IP products. This white paper will explain the concept of the read reorder buffer and explain how a read reorder buffer can improve memory bandwidth. It then concludes with experimental results showing how DRAM controllers with different architectures can achieve vastly different DRAM bus utilizations of 10%, 66%, or 100% from the same input traffic stream, depending on whether the architecture has no RRB, an RRB with external scheduling, or an RRB with content-addressable memory (CAM)-based scheduling.
Marc Greenberg, Product Marketing Director, DDR Controllers, Synopsys



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