Webinars 

Using Foundation IP in Low-Power 40nm IoT Designs
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Kenneth Brock, Product Marketing Manager, Logic Libraries, Synopsys
Jul 21, 2015
 
Automotive Ethernet Moving to Time-Sensitive Environments
Learn about the required network connectivity for automotive applications like ADAS and the importance of integrating Ethernet IP that is certified to be ASIL B Ready for ISO 26262 functional safety.
John Swanson, Product Line Manager, Synopsys
Jul 14, 2015
 
Configure, Integrate & Prototype IP in Minutes
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits , Synopsys
Jun 03, 2015
 
Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015
 
Implementing Next-Generation Vision Capabilities to Enhance Your SoC Designs
Learn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 21, 2015
 
Accelerate DesignWare IP Driver Development for ARMv8-based Designs with Virtualizer Development Kits
Understand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.
Achim Nohl, Technical Marketing Manager, Synopsys
Apr 16, 2015
 
Choosing the Optimal Multiprotocol PHY IP for Your SoC
Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.
Rita Horner, Sr. Technical and Product Marketing Manager, Synopsys
Apr 02, 2015
 
Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Synopsys
Mar 31, 2015
 
Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2015
 
Designing SoCs for USB Type-C Products
Understand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.
Morten Christiansen, Technical Marketing Manager, Synopsys; Gervais Fong, Senior Product Manager, Synopsys
Feb 18, 2015
 
Achieving Energy Efficiency for IoT Designs
Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.
Ron Lowman, Strategic Marketing Manager for IoT, Synopsys
Jan 27, 2015
 
How to Optimize your Application-Specific Processor (ASIP)
Attend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys' ASIP design tool.
Werner Geurts, CAE Manager, Synopsys
Jan 21, 2015
 
FinFETs For Your Next SoC: To Move or Not To Move? (Mandarin)
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Xueheng Ren, Senior Field Application Engineer, Synopsys
Jan 15, 2015
 
Understanding USB 3.1’s Physical, Link & Protocol Layer Changes
Get an in-depth look at the changes in the USB 3.1 specification’s physical layer, link layer, protocol layer, and hub.
Mattew Myers, Sr. Staff R&D Engineer, Synopsys
Jan 13, 2015
 
LPDDR4 Multi-Channel Architecture
Learn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.
Marc Greenberg, Director of Product Marketing for DDR Controller IP, Synopsys
Dec 02, 2014
 
Simplify Sensor and Actuator Functionality for your IoT Solution
Learn how increasing system complexity as sensor fusion functions in IoT apps expand to include biometric control features can be addressed with a tightly integrated sensor and control IP subsystem.
Rich Collins, Product Marketing Manager, Synopsys
Nov 12, 2014
 
High-Speed Embedded Linux Processing on an Embedded Power Budget
This webinar will look at a new high-speed processor implementation that can bring high-performance to your Linux-based embedded designs while significantly reducing power consumption.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Nov 06, 2014
 
Optimizing DSP cores for Performance & Power with DW Logic Libraries & Embedded Memories (Mandarin)
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Wendy Chen, IP Program Manager, Synopsys; Dennis Han, Senior Technical Support Engineer, CEVA
Oct 21, 2014
 
Designing with Non-Volatile Memory for High-Volume Automotive ICs (Mandarin)
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Ming Han, FAE, Synopsys; Ting-Jia Hu, Senior Program Manager, Synopsys
Oct 17, 2014
 
Ethernet in the Connected World
In the connected world, data management and robust networking is essential. Learn about new networking demands for data management between connected devices, market trends and IEEE standards.
John A. Swanson, Product Line Manager, Synopsys
Sep 23, 2014
 
How to Develop Ultra-Low Power Voice Control and Sensor Devices for Always-On IoT Apps
Learn how the efficient response and low power consumption of the ARC® EM DSP processor and Sensory TrulyHandsfree™ software solution deliver excellent performance with long battery life for IoT apps.
Paul Garden, Product Marketing Manager, Synopsys; Bernard Brafman, Vice President of Business Development, Sensory
Sep 18, 2014
 
PCI Express 4.0 & Controller Design: Veni, Vidi, Vici
This technical webinar reviews key changes in the PCI Express 4.0 specification and explains strategies for dealing with digital design challenges, handling the higher bandwidth, and more.
Richard Solomon, Technical Marketing Manager, Synopsys
Sep 16, 2014
 
FinFETs For Your Next SoC: To Move or Not To Move?
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys
Jul 22, 2014
 
Designing with Non-Volatile Memory for High-Volume Automotive ICs
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Angela Raucher, Product Line Manager, Synopsys; Martin Niset Senior R&D Manager, Synopsys
Jul 15, 2014
 
Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
This webinar describes the design challenges and potential advantages of using a multi-protocol 12.5 Gbps PHY that supports a wide range of data rates, features and specifications.
Rita Horner, Product Marketing Manager, Synopsys; Paul Hua, R&D Manager, Synopsys
May 15, 2014
 
Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys;Ran Snir, VLSI Director, CEVA
Apr 24, 2014
 
Case Study: Application-Specific Processors (ASIP) for the Design of Wireless SoCs
In this webinar we will use several real-world examples to highlight why ASIPs can offer computational performance close to fixed-function hardware blocks, providing instruction-level and data-level parallelism, as well as by introducing specialized hardware operators.
Markus Willems, Product Marketing Manager, Synopsys
Apr 15, 2014
 
The Top 5 Features to Consider when Choosing a Platform for SoC Software Development
A complete, standalone platform with all the hardware and software needed for software development, debugging, and profiling will significantly accelerate code development for SoC designs.
Allen Watson, Product Marketing Manager for ARC Development Tools, Systems and Ecosystem, Synopsys
Apr 08, 2014
 
Enrich the Multimedia Experience with HDMI 2.0
Learn about the new HDMI 2.0 specification and how it offers consumers the ultimate home theater experience. This webinar describes the HDMI 2.0 specification, compares it to previous version, and details its new audio, video, and security features.
Manmeet Walia, Senior Product Marketing Manager for DesignWare HDMI IP, Synopsys
Jan 30, 2014
 
Reducing Power Consumption in Mobile Applications with High-Speed Gear 3 MIPI M-PHY IP
This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs.
Hezi Saar, Product Marketing Manager for DesignWare MIPI IP, Synopsys
Jan 22, 2014
 
Optimizing High-End Embedded Designs with High-Performance Processors
Learn about the new DesignWare ARC HS Family of high-end embedded processors and how the processors can be quickly optimized to maximize performance and minimize power.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Dec 12, 2013
 
Enterprise Ethernet IP for Data Center SoC Designs
The Ethernet protocol is evolving to support faster speeds, lower power and smaller area. This webinar reviews the drivers behind the evolution and how DesignWare 40G Ethernet IP meets these demands.
John Swanson, Product Line Manager, DesignWare Ethernet IP, Synopsys
Dec 05, 2013
 
Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC
In this webinar we will describe how the DesignWare STAR Hierarchical System leverages IP and logic block-level test and accelerates SoC testing by enabling faster design closure.
Sandeep Kaushik, Sr. Product Manager, Synopsys
Dec 03, 2013
 
How IP Enables a New Class of SoCs for Data Center Designs
Learn about the latest trends in data center applications such software defined networks and low-power micro servers, and how IP helps address latency, power and RAS requirements for these SoCs.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys
Sep 19, 2013
 
Simplifying Sensor SoC Integration with a Pre-Verified Sensor IP Subsystem
Learn how an integrated, pre-verified sensor IP subsystem consisting of hardware and software eases the integration effort, while offering a 40-60% area savings with lower latency.
Rich Collins, Product Marketing Manager, IP Subsystems, Synopsys
Sep 04, 2013
 
M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs
This webinar describes the M-PCIe ECN and its application space, bandwidth and clocking considerations, the PHY interface, power management, and decisions related to the link-layer changes.
Scott Knowlton, Product Marketing Manager, Sr. Staff, DesignWare PCI Express, PCI-X, PCI and SATA IP, Synopsys; Richard Solomon, Technical Marketing Manager, DesignWare PCI Express Controller IP, Synopsys
Aug 27, 2013
 
Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications
How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.
Martin Niset, Senior Product and Test Engineering Manager, Synopsys
Oct 05, 2011
 
Build low–power, high-performance mobile SoCs with complete MIPI solutions
Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.
Hezi Saar, Product Marketing Manager, Synopsys
Jul 26, 2011
 
Using IP-XACT to Streamline SoC Design and Verification
The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.
John A. Swanson, Senior Manager, Synopsys
Mar 17, 2011
 


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