DesignWare IP White Papers 

Anatomy of the HDMI IP Certification Flow
HDMI IP plays a critical role in enabling HDMI 2.0 features, making 60 frames per second UHD video and audio possible in multimedia SoCs. SoC designers can avoid costly functionality and interoperability issues by selecting and integrating HDMI IP that has gone through an extensive multi-phase testing process and achieved certification. This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).
Dr. Antonio J. Salazar E., ASIC Digital Design Engineer, Synopsys; Hugo Faria, Embedded Software and Protocol Validation Engineer, Synopsys; Quintin D. Anderson, Co-Founder and COO, Granite River Labs

Using an Embedded Vision Processor to Build an Efficient Object Recognition System
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and expanding into emerging high-volume consumer applications such as home surveillance, games, and automotive safety. A major challenge in enabling mass adoption of embedded vision applications is providing the processing capability at a power and cost point low enough for mobile consumer applications, while maintaining sufficient flexibility to cater to rapidly evolving markets. Read this whitepaper to understand the challenges of efficiently implementing an embedded vision system, explore an object detection application example and learn about the DesignWare Embedded Vision Processor Family.
James Campbell, CAE, Synopsys; Valeriy Kazantsev, CAE, Synopsys

Virtualizing Cloud Computing With Optimized IP for NFV SoCs
The growth in internet traffic is impacting how cloud and carrier data center operators design their compute and data networking architectures. To meet the application demands for scale-out servers and networks, designers are implementing virtual environments such as Network Function Virtualization (NFV) to achieve higher efficiency and lower the cost and time of deploying the new applications. This paper discusses how using the right IP accelerates the implementation of SoCs used in NFV systems.
Ron DiGiuseppe, Senior Strategic Marketing Manager, Synopsys

PCI Express 4.0 Controller Design and Integration Challenges
Designers need to start planning for PCI Express 4.0 integration now, because decisions for the PCIe 4.0 controller can have far-reaching consequences for the entire SoC. This paper describes the market adoption and expected use of PCIe 4.0; covers the specification; and discusses three challenges the new specification brings to controller designers.
Scott Knowlton, Sr. Product Marketing Manager, DesignWare Controller IP for PCI Express; Richard Solomon, Sr. Technical Marketing Manager, DesignWare Controller IP for PCI Express

Rapid Architectural Exploration in Designing Application-Specific Processors
Today’s SoCs demand increasing performance with high energy efficiency, but yet require flexibility to address late specification changes, post-silicon modifications and product derivatives. ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP, and efficient architectural exploration is at the heart of any ASIP design process. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain. We will illustrate the architectural exploration approach using a simple yet representative example.
Bo Wu, Technical Marketing Manager, Synopsys; Markus Willems, Product Marketing Manager, Synopsys



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