SoC Infrastructure IP

Accelerating Functional Closure: Synopsys Verification Solutions
This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when and how to implement code and functional coverage, and use it to achieve functional closure.
Hemendra Talesara, Synopsys Professional Services; Neill Mullinger, Synopsys, Inc.

Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare® Interconnect Fabric used to meet the stringent timing requirements.
Fred Roberts, Corporate Applications Engineer, Synopsys, Inc.

Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. This paper, the first in a 2-part series, shows how to start performing constrained random verification quickly and easily with Synopsys' DesignWare VIP and VMM for SystemVerilog.
Charles Li, Corporate Applications, Synopsys, Inc.; Ashesh Doshi, Product Marketing, Synopsys, Inc.

Advanced Techniques for Building Robust Testbenches with DesignWare® Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
This paper is the second in a series and discusses the benefit of using constrained random verification and briefly recaps the first paper "Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Verification Methodology Manual (VMM) for SystemVerilog". The primary focus of the discussion is on using advanced techniques with Synopsys' DesignWare® VIP and VMM for SystemVerilog to build a robust, constrained random testbench. The techniques that will be discussed are: Constraints, Factories, Callbacks, Coverage and Scenario Generation.
Charles Li, Corporate Applications, Synopsys, Inc.; Ashesh Doshi, Product Marketing, Synopsys, Inc.

Advanced Stimulus Generation with DesignWare Verification IP and Verification Methodology Manual for SystemVerilog
This paper shows how to perform advanced stimulus generation using DesignWare Verification IP (VIP) and Verification Methodology Manual (VMM) for SystemVerilog. It focuses on two key topics - Exceptions and Scenario Generation. Exceptions represent protocol deviations or injected errors. The ability to create scenarios with Scenario Generation, which are sequences of protocol activity, is the key to effectively testing and verifying the design. This paper goes into the details of successfully creating exceptions and generating scenarios.
Charles Li, Corporate Applications, Synopsys, Inc.

Coding Guidelines for Datapath Synthesis (Aug. 2009)
This document summarizes coding guidelines addressing the synthesis of datapaths. Two classes of guidelines are distinguished: 1) Guidelines that help achieve functional correctness and the intended behavior of arithmetic expressions in RTL code; and, 2) Guidelines that help datapath synthesis to achieve the best possible quality of results (QoR).
Reto Zimmerman, Principal Engineer, Synopsys, Inc.

IP Solutions for Synchronizing Signals that Cross Clock Domains
This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another. In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another. Along with each issue, one or more DesignWare® solutions are outlined. The topics and solutions include: basic synchronization; temporal event synchronization; simple data transfer synchronization; data flow synchronization; reset sequencing; and, related clock system data synchronization.
Rick Kelly, R&D Manager, Synopsys, Inc.

Implementing Floating-Point IP for the Right Accuracy and Quality of Results (QoR)
With a rich library of DesignWare® Floating-Point IP, chip designers have many implementation choices that can significantly affect the final QoR. These choices are especially important when using synthesizable IP, where good implementation choices can optimize the tradeoffs between area/delay and accuracy. This whitepaper describes several types of flexible tradeoffs available to designers, including the benefits of specifying complex floating-point operations rather than multiple separate operations.
Alex Tenca, Engineering Project Leader, Synopsys, Inc.

Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP
To successfully develop an AMBA 3 AXI protocol-based design in the shortest time requires a comprehensive set of synthesizable IP, verification IP and an automated method to assemble the entire SoC subsystem. The AMBA 3 Advanced eXtensible Interface (AXI) protocol builds on the benefits of the AMBA 2.0 standard offering greater performance and flexibility. But with this flexibility comes complexity. This paper shows how the DesignWare IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate high speed designs based on the AMBA 3 AXI protocol.
Mick Posner, Product Marketing Manager, Synopsys, Inc.

Designing Using the AMBA 3 AXI Protocol
This paper examines the advantages of the new AMBA 3 Advanced eXtensible Interface (AXI) protocol for an on-chip bus infrastructure, and how it revolutionizes the future of high-performance system-on-chip (SoC) interconnect. It also describes the AMBA 3 AXI protocol feature set that makes it suitable for the new high-performance, low-latency and low-power designs.
Mick Posner, Product Marketing Manager, Synopsys, Inc.; Darrin Mossor, Synopsys, Inc.

Coding Guidelines for Datapath Synthesis
This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths. The first class helps achieve functional correctness and intended behavior of arithmetic expressions in RTL code. The second helps datapath synthesis to achieve best possible quality of results (QoR).
Reto Zimmermann, Principal Engineer, Synopsys, Inc.



NewsArticlesBlogsWhite PapersWebinarsVideosNewslettersCustomer Successes