|Using an Embedded Vision Processor to Build an Efficient Object Recognition System|
The advent of high-performance mobile computing platforms is driving rapid progress in computer vision capabilities. Machine vision is becoming embedded in highly integrated SoCs and expanding into emerging high-volume consumer applications such as home surveillance, games, and automotive safety. A major challenge in enabling mass adoption of embedded vision applications is providing the processing capability at a power and cost point low enough for mobile consumer applications, while maintaining sufficient flexibility to cater to rapidly evolving markets. Read this whitepaper to understand the challenges of efficiently implementing an embedded vision system, explore an object detection application example and learn about the DesignWare Embedded Vision Processor Family.
James Campbell, CAE, Synopsys; Valeriy Kazantsev, CAE, Synopsys
|Rapid Architectural Exploration in Designing Application-Specific Processors|
Today’s SoCs demand increasing performance with high energy efficiency, but yet require flexibility to address late specification changes, post-silicon modifications and product derivatives. ASIPs close the gap between highly optimized fixed-hardware data path implementations and standard processor IP, and efficient architectural exploration is at the heart of any ASIP design process. Designers need to rapidly explore the impact of different architectural choices on power consumption and performance, ideally using real-world application C-code as part of the design flow. This white paper explains the architectural tradeoffs that are available to an ASIP designer, how to trade off performance vs. area, and why an ASIP design can still maintain full C-programmability while being optimized for a certain application domain. We will illustrate the architectural exploration approach using a simple yet representative example.
Bo Wu, Technical Marketing Manager, Synopsys; Markus Willems, Product Marketing Manager, Synopsys
|Real-Time Trace: A Better Way to Debug Embedded Applications|
Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This whitepaper shows the benefits of debugging with ‘real-time trace’ hardware assistance, including how it can vastly reduce the amount of time needed to track down problems in the code, and introduces other benefits, such as hot-spot profiling and code coverage, offered by real-time trace systems.
James Campbell, CAE, Synopsys, Inc.; Valeriy Kazantsev, CAE, Synopsys, Inc.; Hugh O’Keefe, Engineering Director, Ashling Microsystems
|Designing Application-Specific Processors for Wireless Baseband SoCs|
Traditional architectures for wireless baseband applications are no longer adequate for next-generation modem standards. Supporting multiple, evolving standards in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which allows design teams to better optimize their design’s wireless baseband SoCs. This white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.
Bo Wu, Technical Marketing Manager, Synopsys, Inc.
|ARC HS38: Single- and Multicore CPUs for High-Speed Linux Processing on an Embedded Budget|
This white paper describes the Synopsys DesignWare® ARC® HS38 multicore processor for embedded Linux applications. The ARC HS38 processor is the latest addition to the ARC HS Family and adds several features including MMU, cache coherent symmetric multiprocessing and L2 cache. This whitepaper describes the key HS38 features for delivering high speed of operation with exceptional code density and power efficiency. Other topics covered include dual- and quad-core configurations, configurability options and instruction set architecture (ISA) extensibility that is unique to the ARCv2 architecture. This report was prepared by the Linley Group based on their analysis for the HS38 Processor.
Tom R. Halfhill, Senior Analyst, The Linley Group
|Designing ASIPs in Multicore SoCs|
Modern SoCs integrate dozens of complex system functions, each requiring its own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of fixed hardware accelerators no longer suffices. Application-specific instruction-set processors (ASIPs) can offer the best balance for each system function, and thus form the basis of new generations of multicore SoCs. ASIP design requires tools and methodologies that enable fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification. Any ASIP design approach has to support a broad range of architectures, from small microprocessors, over DSP dominated cores, to VLIW and vector processors.
Gert Goossens, R&D Director; Dirk Lanneer, R&D Manager; Werner Geurts, CAE Manager; Johan Van Praet, R&D Manager, Synopsys
|Building an Efficient, Tightly Coupled Embedded System Using an Extensible Processor|
The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems, which has caused the power, performance and area (PPA) ratio of these systems to also shift in favor of performance at the cost of power and area. Closely coupled memories, together with ARC Processor EXtension (APEX) technology, provide a means to tightly couple memories and peripherals to an ARC processor core and make the area- and latency-expensive bus infrastructure redundant, reducing both the power consumption and area costs of the embedded system without sacrificing performance.
Jeroen Geuzebroek, Sr. R&D Engineer, Synopsys; Ad Vaassen, Sr. System Engineer, Synopsys
|Ultra Low-Power 9D Sensor Fusion Implementation|
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that converts inputs from multiple motion sensors into accurate position information. This computation is called sensor fusion and it eliminates inaccuracies from noisy sensor inputs. This paper shows how using ARC Processor EXtension (APEX) technology improves cycle count and energy consumption for a power-efficient implementation of a 9D fusion algorithm on an IP subsystem.
Pieter Struik, R&D Engineer, Sr. Staff, Synopsys
|Leveraging Processor Extensibility to Build an Ultra Low-Power Embedded Subsystem|
The ever increasing demand for smaller electronic devices, with more functionality, longer battery life, and shorter time to market has accelerated use of embedded processors and subsystems to offload the host processor from commonly executed tasks. Processor extensions provide a means to extend a general-purpose processor with custom hardware accelerators to optimize the execution of dedicated applications for reduced energy consumption and area, and/or increased performance. This white paper describes how processor extensions can optimize power and performance of a processor when targeting sensor applications, demonstrated using Synopsys’ DesignWare® ARC® Processors and ARC Processor Extensions (APEX) technology.
Jeroen Geuzebroek, Senior R&D Engineer, Synopsys
|The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications|
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group
|The Linley Group: DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications|
This paper describes Synopsys’ DesignWare® ARC® EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores.
J. Scott Gardner, Senior Analyst, The Linley Group; Tom R. Halfhill, Senior Analyst, The Linley Group
|Obfuscating Attacks on Secure SoCs through Encrypted Code Execution|
Security concerns continue to prevail in a wide variety and growing number of application areas for SoCs, with attacks commonly targeting memory contents and processor operation. Secure SoCs, such as those commonly found in payment cards, often come under various forms of attacks from hackers seeking to access the information stored in the on-chip memories and use it for illegal financial gain. As a result, security schemes must be varied and many, while limiting cost and performance impact. By enabling on-the-fly execution of encrypted code, the ARC Secure option for DesignWare ARC 600 processors ensures that attacks accessing instruction memory contents find encrypted code, and attacks focused on processor operational signatures (such as state or state changes) are more difficult to carry out.
Steve Tateosian, Synopsys, Inc., Product Marketing Manager
|Improving Performance and Simplifying Coding with XY Memory’s Implicit Parallelism|
Explicit and implicit instruction-level parallelism techniques boost processor performance by increasing the amount of work done in a given time interval. Implicit parallelism using XY memory retains the RISC programming model and brings all the XY memories into the pipeline, resulting in a resource-efficient and high-performing implementation. The DesignWare® ARC™ XY Advanced DSP extension adds digital signal processing to the ARC processors, enabling RISC and signal processing computation within a single unified architecture.
Manny Wright, Senior FAE, Synopsys, Inc.
|Reality Check: A Guide to Understanding Optimized Processor Cores|
The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation for your application.
Jonathan Young, Brian Machesney, Synopsys, Inc.