This paper describes Synopsys’s DesignWare® ARC™ EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores. This paper is sponsored by Synopsys, but all opinions and analysis are those of the author.
J. Scott Gardner, Senior Analyst, The Linley Group

Security concerns continue to prevail in a wide variety and growing number of application areas for SoCs, with attacks commonly targeting memory contents and processor operation. Secure SoCs, such as those commonly found in payment cards, often come under various forms of attacks from hackers seeking to access the information stored in the on-chip memories and use it for illegal financial gain. As a result, security schemes must be varied and many, while limiting cost and performance impact. By enabling on-the-fly execution of encrypted code, the ARC Secure option for DesignWare ARC 600 processors ensures that attacks accessing instruction memory contents find encrypted code, and attacks focused on processor operational signatures (such as state or state changes) are more difficult to carry out.
Steve Tateosian, Synopsys, Inc., Product Marketing Manager

Explicit and implicit instruction-level parallelism techniques boost processor performance by increasing the amount of work done in a given time interval. Implicit parallelism using XY memory retains the RISC programming model and brings all the XY memories into the pipeline, resulting in a resource-efficient and high-performing implementation. The DesignWare® ARC™ XY Advanced DSP extension adds digital signal processing to the ARC processors, enabling RISC and signal processing computation within a single unified architecture.
Manny Wright, Senior FAE, Synopsys, Inc.

The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation for your application.
Jonathan Young, Brian Machesney, Synopsys, Inc.