|Technical Considerations for Implementing USB 3.0 on SoCs|
This paper highlights the specific features and enhancements in the USB 3.0 protocol. These
enhancements come with technical complexities, and this paper outlines complexities and the resulting
design challenges. It shows how a USB 3.0 core's reconfigurability can broaden a design's potential
applications and reuse. Finally, it talks about USB 3.0 selection and implementation considerations, from
architecture, prototyping, and software, to testing and certification.
Gervais Fong, Senior Product Marketing Manager, Synopsys, Inc.; Eric Huang, Senior Product Marketing Manager, Synopsys, Inc.
|Shrinking SoC Design Cycles Using DesignWare Intellectual Property|
In this case study, it was discussed how DesignWare IP was leveraged, including USB 2.0 host, USB 2.0 Hi-Speed OTG, Ethernet Controller and SATA, to meet key requirements of IP integration, verification and synthesis to complete a successful design in a short design cycle. The results are highlighted, discussing the issues and the methodology that can be used to achieve the most out of these DesignWare IP solutions, resulting in a reduced SoC design cycle.
Vijay Kumar Mathur, ST Microelectronics; Gaurav Bhatnagar, ST Microelectronics; Rohitaswa Bhattacharya, ST Microelectronics
|Ethernet Quality-of-Service: New IEEE Specifications Driving a New Generation of Network Products|
As designers look to their next-generation network designs, they are faced with a set of new challenges when developing products that incorporate the common Ethernet interface. To maintain Ethernet as a dominate and long-lasting network interface, the latest IEEE updates, which are targeted at improving networking systems' Quality-of-Service, will be critical to meet the demands of the consumer.
Lokesh Kabra, Senior R&D, Manager, Synopsys, Inc.; John A. Swanson, Senior Staff, Marketing Manager, Synopsys, Inc.
|Debugging SuperSpeed USB Software Using Virtual Prototypes|
Software is a critical component for the development of USB-based designs. In efforts to start software development early and to make it as productive as possible, design teams are often utilizing virtual and FPGA prototypes for software development prior to silicon. This white paper describes how virtual prototype use models for hardware/software verification and the integration of the LeCroy analyzer software into Synopsys' DesignWare SuperSpeed USB verification environments help solve SuperSpeed USB IP development challenges.
Frank Schirrmeister, Director, Product Marketing; Tri Nguyen, R&D Engineer, Synopsys, Inc.
|Improving I/O Virtualization Performance with PCI Express|
This paper provides an introduction to the general concepts of virtualization and I/O virtualization (IOV). It also discusses how IOV is addressed within the PCI Express sepcification and how to support IOV with an existing PCIe interface. Additional topics include: Single-Root IOV, Function Level Reset, Alternative Routing ID and Address Translation Services.
Scott Knowlton, Sr. Product Marketing Manager, Synopsys, Inc.
|SuperSpeed Your SoCs with USB 3.0 IP|
This whitepaper provides a comparison between the USB 3.0 and USB 2.0 standards, highlighting the new capabilities and advancements that have been made with this next-generation SuperSpeed USB standard including: performance, cables and connectors, power efficiency, USB model differences, hardware and software functionality, new protocol layers and streaming.
Dr. Robert Lefferts, R&D Director, Synopsys, Inc.; Subramaniam Aravindhan, R&D Manager, Synopsys, Inc.
|Show Me the Next-Generation HDMI|
Explore the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. In addition, this paper provides a tutorial on the new capabilities of HDMI 1.4 and its role in providing a richer, more straightforward user experience. Example case studies are also presented to illustrate how the HDMI Ethernet and Audio Return Channel (HEAC) feature simplifies cabling requirements.
Manmeet Walia, Product Marketing Manager, Synopsys, Inc.
|DesignWare SATA AHCI Host Controller - Understanding Multi-Port Configuration and Performance|
This whitepaper describes how to configure and connect the DesignWare® SATA AHCI IP core to the DesignWare SATA PHY in a multi-port AHB-based configuration. It provides an analysis of the expected throughput on each port based on assumed system parameters. The intent of this paper is to enable users to take this example and insert actual system parameters to come up with a performance estimate.
Bjorn Widerstrom, Corporate Applications Engineer, Synopsys, Inc.
|Embedded DDR Interfaces: Ten Tips to Success for Your SoC|
Emerging from a host of competing technologies, DDR2 and DDR3 SDRAM ("DDR") have become the dominant off-chip memory storage solution for SoC designs. Unfortunately, many SoC designers are unfamiliar with the realities of the DRAM standards, typical DRAM applications and the DRAM market. This paper presents ten guiding principles for embedded DDR interfaces, many of which the DRAM standards and vendor data sheets do not explain.
Graham Allan, Sr. Product Marketing Manager, Synopsys, Inc.
|Enabling Portable, Lower Power HDMI-Based Designs with Interface IP|
By using IP, SoC designers can easily incorporate an HDMI interface in leading edge process technologies such as 90 nanometer (nm), 65 nm and 40 nm processes. This eliminates the need for a separate IC, delivering significant power and cost savings. This paper provides an overview of HDMI standard , how it’s different from other digital video connections and the advantage of incorporating it into your SoC.
Luis Laranjeira, Sr. R&D Manager, Synopsys, Inc.
|Meeting Timing Budgets for DDR Memory Interfaces|
This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains. It shows how designers can meet timing budgets for double data rate, single data rate and cross-domain (clock-to-strobe) timing domains. Finally, it shows how to improve interconnect timing by reducing crosstalk, inter-symbol interference, reflections and skew as well as controlling simultaneously switching output (SSO) effects.
John Ellis, Senior Staff R & D Engineer, Synopsys, Inc.
|Solving the Integration Challenges for USB-Enabled Designs|
With power consumption and small form factors key issues, SoC designers must consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP offerings available from Synopsys.
Gervais Fong, Product Marketing Manager, Synopsys, Inc.;
Eric Huang, Product Marketing Manager, Synopsys, Inc.
|Understanding the Fundamentals of PCI Express|
PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP). The objective of this white paper is to equip the reader with a broad understanding of the PCI Express standard, and the design challenges associated with implementing the PCI Express interface into an SoC.
Scott Knowlton, Product Marketing Manager, Synopsys, Inc.
|DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs|
As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2 and DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues. In this paper, learn about the ins and outs of the DDR interface.
Graham Allan, Senior Product Marketing Manager, Synopsys, Inc.
|High Performance Connectivity IP: Avoiding Pitfalls When Selecting an IP Vendor|
The demand for connectivity IP for high-speed serial busses such as USB 2.0, PCI Express®, SATA, DDR2 and HDMI is increasing as standard interfaces in applications such as single chip recordable DVD CODECs and MP3 players. In order to stretch battery life of these chips, the semiconductor technologies require ultra-low power derivatives of high-performance logic manufacturing processes, enabling production of very low-power chips for these mobile platforms and small-form factor devices.
Navraj S. Nandra, Director of Product Marketing, Synopsys, Inc.
|Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design|
This paper discusses how using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks, such as interoperability, associated with combining discrete memory subsystem blocks.
David Wallace, Product Marketing Manager, Synopsys, Inc.
|Low Power USB 2.0 PHY IP for High-Volume Consumer Applications|
The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB IP this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted at mobile and high volume consumer applications. This offers designers a choice of highly differentiated USB PHY cores for 0.13-micron processes and below.
Gervais Fong, Product Marketing Manager, Synopsys, Inc.
|How A Complete IP Solution Speeds Time-to-Market and Reduces Risk for 10 Gigabit Ethernet Applications|
This paper discusses the merits of IP for the growing 10G Ethernet market, and introduces Synopsys' complete DesignWare® 10G Ethernet IP solution in the context of the technology and the target applications. It provides an overview of the market growth trends and highlights typical application areas for 10G Ethernet.
Geetha R. Arun, Program Manager, Synopsys, Inc.
|Agere/Synopsys: Integrating a PCI Express Digital IP Core into a Gigabit Ethernet Controller|
This paper discusses the integration and system verification challenges encountered when integrating a PCI Express digital IP core into a Gigabit Ethernet design. Techniques for configuration of the PCI Express IP toachieve the lowest power, lowest latency and smallest memory size, as well as optimal system performance are presented
Jing-Fan Zhang, Director, Business Development, Synopsys, Inc.;
Fadi Saibi, Sr. Member of Technical Staff, Agere Systems