Analog IP

Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond
This white paper compares the attributes of common ADC architectures, including the Successive Approximation Register (SAR)-based architecture, for use in medium- and high-speed 28-nm ADCs. It describes advantages of the SAR-based architecture that reduce power consumption and area usage for mobile and multimedia SoCs. Finally, it presents the DesignWare SAR-based ADC family for 28-nm and explains how it benefits from advanced process nodes through adherence to the area and power scaling paradigms of digital circuitry.
Carlos Azeredo-Leme, Analog Design, Senior Staff, Synopsys, Inc.; Pedro Figueiredo, Analog Design, Staff, Synopsys, Inc.; Manuel Mota, Technical Marketing Manager, Synopsys, Inc.

Twelve Design Techniques for Successful Integration of Data Converter IP into an SoC
Data converter IP integration is sometimes perceived as complex because it requires careful custom place-and-route. However, by understanding the potential issues that can impact performance, an SoC designer has all the tools for successful integration that delivers the expected performance. This white paper provides twelve simple design techniques that address all the common issues of integration in a methodical way and help ensure the successful integration of high-performance data converters in SoCs.
Roberto Guerreiro, Application Engineering Manager, Synopsys, Inc ; Manuel Mota, Technical Marketing Manager, Synopsys, Inc.

Implementing Audio Codecs in 28-nm Mobile Multimedia Advanced SoCs
This paper discusses the main system and technical challenges of integrating audio functionality in 28-nm mobile multimedia SoCs and how to address these challenges through different techniques. These techniques include: taking advantage of Moore's Law and moving functionality to the digital domain, designing in flexibility for the multitude of clock rates, managing performance trade-offs of reduced supply voltages, and exploring system partitioning outside of the SoC.
Carlos Azeredo-Leme, Analog Design, Senior Staf, Synopsys, Inc.; Craig Zajac, Senior Product Marketing Manager, Synopsys, Inc.

Unleash the Performance Benefits of Sigma-Delta ADCs into Your SoC: IP supports cellular communications, sensors and measurement markets
Sigma-delta analog-to-digital converters (ADCs) deliver high resolution with low silicon area and power consumption, taking advantage of high-speed operation and digital signal processing common in modern digital system-on-chip (SoC), making them ideal for implementations in deep sub-micron processes. However designers are sometimes reluctant to use sigma-delta ADCs because of their unconventional architecture and apparently chaotic internal operation. This paper will give SoC designers a clear understanding of the workings inside sigma-delta ADCs and explain when they are a better alternative than other ADC architectures used in advanced, deep sub-micron SoCs.
Carlos Azeredo-Leme, Analog Design, Senior Staff, Synopsys, Inc.

Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP
To optimally address all the requirements for each application, there is a new generation of advanced data converter IP that includes Nyquist rate high-performance, high-speed ADC products, based on a highly optimized pipeline architecture. This paper describes the main power versus resolution trade-offs existing in the design of pipeline ADCs. It also discusses how digital gain calibration - one of the key techniques employed - eases those trade-offs, thus achieving significant improvements in power and area.
Pedro Figueiredo, Staff Engineer, Data Conversion, Synopsys, Inc.

Simple Ways to Manage Different Clock Frequencies of Audio Codecs
The audio codec creates the interface between the digital host processor and the audio transducers, such as microphones and speakers. When embedded in a SoC as an IP core, an audio codec appears as a digital block to the internal interfaces and transparently handles all the off-chip analog transducers and inputs/outputs. On the internal digital interface, it is important to understand the aspects relating audio sample rates and clocks. The clocks required by the data converters on an audio codec depend on the audio material sampling rates as well as on the clocks available on the host application and SoC. The combinations are quite complex due to the multitude of audio sample rate options and available host clocks. To further complicate matters, in audio-video applications, the audio clocks need to also be synchronized with the video clocks required by the video data converters. The digital filters process the digital samples between the digital audio interface and the audio data converters, and therefore, can perform sampling rate conversions. This paper will review the functions of digital filters in audio codecs and will illustrate how they can be used to support interfacing in a multitude of sample-rates and clock environments.
Carlos Azeredo-Leme, Analog Design, Senior Staff, Synopsys, Inc.

Sweet Sounding SoCs: Why Analog Audio IP Lowers Costs and Sounds Better than Digital PWM
When determining the trade-offs between application requirements versus area and power, selecting the right audio drivers has become a critical decision for SoC designers. Audio drivers must efficiently address a wide variety of loading conditions such as line loads, earphone and headset loads, passive loudspeaker loads and more. For many years, solutions consisting of a digital-to-analog converter and continuous time drivers have co-existed with digital-centric Pulse Width Modulation (PWM)-based solutions to address the breadth of different audio loads. Perhaps the most important reason associated with choosing a digital-centric PWM-based solution is the perception that being purely digital its silicon area cost is lower than the analog implementations. However, this whitepaper shows that digital-centric PWM-based solutions do at most offset cost from silicon area to external components while failing to address a multitude of equally important application requirements besides low cost.
João Risques, Product Marketing Manager, Synopsys, Inc.

Understanding Clock Jitter Effects on Data Converter Performance and How to Minimize Them
This white paper shows that the characteristics of the sampling clock may determine the system performance, and that their effect is independent of the data converter that is being used in the system rather being a function of the characteristics of the signal being processed by the system (for example, its frequency). It also identifies the main sources of this clock uncertainty (clock jitter effects), providing guidelines and rules for system engineers to understand and minimize such effects, thus assuring system performance requirements.
Manuel Mota, Technical Marketing Manager, Synopsys, Inc.

High Definition Video AFE: Far Beyond the ADC
Based on the importance of the video AFE as an essential part of nearly any consumer video product or personal computing display and on the need that these products deliver the highest-quality images, this paper explains that, although it is possible to implement a video AFE from a stand-alone ADC and a collection of separate analog components, the complex interactions between them make developing an optimized system a difficult task which can add significant delay and risk to a design cycle. These risks can be reduced using an optimized video AFE core from a third party IP provider ensuring your design delivers the best possible video quality and power efficiency in all of the operating modes.
João Risques, Product Marketing Manager, Synopsys, Inc.

Reverse Process Migration from 65nm to 130nm in Under Three Months
Normally, a design team will tackle a new project on a new, smaller-geometry process and realize the benefits of increased performance and lower cost per chip. This white paper addresses the reverse of this situation, in which a functioning 65nm analog and mixed-signal design is “blown up” to a 130nm process to help mitigate the higher mask costs of the smaller geometry.
Bob Lefferts, R&D Group Director, Analog and Mixed-signal IP, Synopsys, Inc.; Neel Gopalan, AMS CAE, Synopsys, Inc.

Hi-Fi Audio: Unveiling the Hidden dBs
While looking at Hi-Fi Audio, high “dynamic range” is the most popular measurement used to assess whether an audio system is "clean" (providing high-quality audio experience), but should not be the only area of focus. This paper discusses dynamic range, the specification and hidden dBs that should be considered for the best audio experience possible.
Joao Risques, Product Marketing Manager, Synopsys, Inc.

How System-Level Trade-offs Drive Data Converter Decisions
For both analog-to-digital converters (ADC) and digital-to-analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter's design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter's sampling rate to the choice of single- or multiple-chip system partitioning.
Manuel Mota, Technical Marketing Manager, Synopsys, Inc.



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