|Faster SoC Bring-Up and Configuration with DesignWare IP Prototyping Kits|
DesignWare IP Prototyping Kits enable earlier software development, easier IP integration, and faster IP prototyping for both hardware and software engineers. See how quickly you can kick-start your design with the included reference designs, then reconfigure the IP for your application and develop embedded software in real-time.
Asheesh Khare, Sr. Staff FAE Manager
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|Featured PCIe Video: Industry First: PCI Express 4.0 Controller IP|
Synopsys demonstrates the industry’s first PCI Express 4.0 Controller IP at PCI-SIG 2014. Using coreConsultant, designers can configure the DesignWare PCIe 4.0 IP for their specific SoC requirements, including 16 Gbps data rates.
Paul Cassidy, R&D Manager, PCIe, Synopsys
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|Physical IP Development on FinFET - There's Nothing Planar About It! (12:30-2:00)|
This video discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries, Synopsys
||New DesignWare® USB 3.0 & 2.0 femtoPHY IP: FinFET Silicon Success|
View the silicon test results of the new DesignWare USB femtoPHY family. DesignWare USB 3.0 and 2.0 femtoPHYs, available now on leading FinFET process technologies, reduce USB area by 50% compared to previous generations.
Sr. Product Marketing Manager, USB IP
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|Featured HDMI Video: Synopsys Demonstrates DesignWare HDMI 2.0 IP Solution|
Join us in the Synopsys HDMI lab to see a demo of our HDMI 2.0 transmitter and receiver performance and features such as 4K video, YCbCr 4:2:0 colorimetry, and the HDCP 2.2 content protection standard.
Luis Laranjeira, R&D Manager, Synopsys
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|Featured MIPI Video: Synopsys Demonstrates DesignWare UFS Host and MIPI UniPro IP Interoperability|
Synopsys plays a key role in supporting the mobile ecosystem by delivering high-quality, interoperable MIPI IP solutions that enable designers to deploy new features into their next-generation mobile devices, as demonstrated at Mobile World Congress 2014. This demonstration showcases the DesignWare® UFS Host and MIPI UniPro IP solutions' proven system-level interoperability.
Hezi Saar, Product Marketing Manager for MIPI IP, Synopsys and Philippe Borges, Field Applications Engineer, Synopsys
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|Synopsys Launches DesignWare ARC Software Development Platforms|
Learn how Synopsys’ new DesignWare® ARC® Software Development Platforms help designers accelerate software development for their ARC processor-based designs. These ready-to-use, integrated hardware and software platforms provide software developers an out-of-the-box solution that incorporates the hardware and software needed to significantly accelerate the code development, including silicon-proven ARC processors, peripheral I/O, operating systems and drivers, all on a single, integrated platform.
Allen Watson, Product Marketing Manager, ARC Tools, Synopsys
|Featured Ethernet Video: Reducing EMI in SerDes PHYs using Spread Spectrum Clocking|
Learn what spread spectrum clocking (SSC) is and why it is important to high-speed SerDes design.
John Stonick, Synopsys Fellow, Solutions Group, Synopsys and Rita Horner, Sr. Technical Marketing Manager, Mixed Signal IP, Synopsys
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|Synopsys’ New DesignWare ARC HS Processors for Next-Generation Embedded Systems|
Learn about Synopsys’ new DesignWare® ARC® HS processors, a new family of 32-bit high-speed, low-power processors optimized for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm²).
Mike Thompson, Sr. Product Marketing Manager, ARC Processors, Synopsys
|Introducing the DesignWare Sensor IP Subsystem|
Learn more about the complete DesignWare® Sensor IP Subsystem, an integrated, pre-verified hardware and software solution targeted for a broad range of sensor control applications such as smart sensors, sensor fusion, and sensor hub.
Rich Collins, Product Marketing Manager, Synopsys
|Designing IP for FinFET Technology: The Opportunities and Challenges|
FinFETs are emerging as the device technology of choice at advanced nodes. This introduces new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This video describes the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.
Jamil Kawa, R&D Director, Synopsys
|Featured DDR Video: Synopsys Discusses its New DDR4 Memory Interface IP|
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean OKane, ChipEstimate.com
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|Featured SATA Video: SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching|
See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys
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|Featured Analog Video: Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution|
Synopsys shows the next generation DesignWare ADC IP 12-bit 250 MSPS, delivering outstanding performance, robustness and ultra low power dissipation of up to 50% less than previous generations.
Manuel Mota, Technical Marketing Manager, Synopsys and José Carmo, Application Engineer, Synopsys
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|Introducing the DesignWare HPC Design Kit|
Learn how Synopsys' DesignWare HPC Design Kit, a single package containing high-speed and high-density memory instances and standard cell libraries, allow designers to optimize all their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power. Hear about the results achieved on the Imagination PowerVR™ Series6 GPU core.
View more DesignWare Embedded Memories, Logic Libraries and Embedded Test Videos>
|Industry’s First Complete Audio IP Subsystem|
Learn how the pre-integrated, configurable DesignWare® SoundWave Audio Subsystem helps you achieve great audio with a complete, SoC-ready subsystem solution. Also, join us in the Synopsys Sound Room, where we test our high-definition audio solutions, to see the SoundWave Audio Subsystem in action using a HAPS® FPGA-Based Prototyping System.
Henk Hamoen, Sr. Product Marketing Manager, Synopsys