| May 14, 2012 | AMD Selects Synopsys as a Verification IP Partner
Expands Collaboration to Further Accelerate SoC Verification
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| Mar 26, 2012 | Synopsys Unveils Industry's First Complete Audio IP Subsystem
Integrated, Configurable Hardware and Software Solution Enables "Drop-in" Audio Functionality Supporting Latest Audio Standards
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| Mar 22, 2012 | Synopsys Extends Leadership in Storage Standards Verification IP with NVM Express
Offers First-to-Market VIP for the Emerging NVMe Storage Interface Protocol
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| Mar 13, 2012 | GUC and Synopsys Achieve Design Milestone
High-quality IP, 30 customer tape-outs contribute to Flexible ASIC success
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| Feb 28, 2012 | Synopsys Introduces Industry's First 28-nm Multi-Gear MIPI Alliance M-PHY IP Supporting Six Standards for Mobile Applications
Scalable DesignWare MIPI M-PHY IP future-proofs mobile SoC designs while providing low power, low latency and compact footprint
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| Feb 28, 2012 | Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs
Joint MIPI Alliance Low Latency Interface (LLI) IP solution enables lower bill of materials cost and smaller printed circuit board area for mobile phones
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| Feb 14, 2012 | Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
Advanced Memory and Logic IP Enable Designers to Optimize 28-nm SoCs for Both Maximum Performance and Low Power Consumption
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| Feb 13, 2012 | Synopsys Announces Industry's First HDMI 1.4 PHY IP in 28-nanometer Processes for Multiple Foundries
Silicon-proven DesignWare HDMI IP Enables Designers to Achieve Power and Performance Goals for Advanced Mobile Multimedia and Digital Home Designs
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| Nov 07, 2011 | Synopsys Awarded TSMC's Interface IP Partner of the Year
Technology Leadership and Outstanding Customer Support Cited as Key Selection Criteria
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| Oct 26, 2011 | Synopsys' DesignWare Audio IP Achieves First-Pass Silicon Success in Leading 65-nm and 55-nm Process Technologies
High-performance, Low Power DesignWare 96 dB Hi-Fi Audio IP Optimized for Mobile Multimedia and Digital Home SoC Applications
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| Oct 11, 2011 | UMC and Synopsys Collaborate to Develop DesignWare IP for 28-nanometer Technology
Collaboration on Embedded Memory and Logic Library for UMC’s Enhanced Poly SiON HLP Process Enables Creation of High-Performance, Low-Power SoCs
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| Oct 03, 2011 | Synopsys' DesignWare SuperSpeed USB 3.0 IP Achieves More Than 40 Design Wins
Selected by More Than 30 Customers, Silicon-Proven USB 3.0 IP Lowers Integration Risk
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| Sep 20, 2011 | Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips
Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories
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| Jun 27, 2011 | Synopsys Announces Immediate Availability of Reprogrammable Non-Volatile Memory IP in 180-nm CMOS Process Technology
DesignWare AEON Embedded Non-Volatile Memory IP Improves Electrical Performance and Lowers Integration Risk for Wireless and Analog SoC Designs
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| May 12, 2011 | Synopsys' DesignWare SATA 6Gb/s IP Solutions Receive SATA-IO Certification
Silicon-Proven DesignWare Controllers and PHY IP Lower Design Risk and Speed Adoption of SATA 6G Functionality and Data Transfer Rates
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| May 11, 2011 | Synopsys DesignWare ARC Sound IP Solution First to Support the Dynamic Resolution Adaptation Audio Standard
DesignWare ARC Sound DRA Decoder Supports the Chinese National High-Definition Audio Standard and Enables an Enhanced, High-Quality Audio Experience
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| May 05, 2011 | Synopsys' DesignWare SuperSpeed USB 3.0 xHCI Host Controller IP Receives USB-IF Certification
Silicon-Proven DesignWare IP Lowers Design Risk and Allows Interoperability with USB 3.0-Enabled Products
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| Mar 31, 2011 | Fairchild Semiconductor Achieves First-Pass Silicon Success with DesignWare USB 2.0 nanoPHY IP
High-Quality USB 2.0 IP Reduces Integration Risk and Helps Meet Critical Low Power and Area Requirements for Complex SoC Design
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| Mar 30, 2011 | Synopsys Announces Availability of DesignWare PHY and Embedded Memory IP for TSMC Advanced 28-nanometer Technologies
Achieving USB Logo Certification for DesignWare USB 2.0 picoPHY Demonstrates Success of Collaboration
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| Mar 23, 2011 | Freescale Licenses Synopsys' DesignWare IP Portfolio to Accelerate SoC Designs
High-Quality, Broad Portfolio and Worldwide Technical Support Helps Freescale Speed SoC Development Time and Lower Risk
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| Mar 22, 2011 | Wilocity Tapes-Out Multi-Gigabit Wireless Communication SoC Using Synopsys DesignWare IP
High-quality DesignWare IP Combined with Professional Services Speeds Development Time and Lowers Integration Risk for Wireless Gigabit Alliance SoC
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| Mar 21, 2011 | Synopsys' Next-Generation DesignWare Data Converter IP Delivers 50 Percent Lower Power with Smaller Area
High-performance 10/12-bit ADCs and 14-bit DACs Enable Easy Integration into Broadband Wireless and Wireline Communication SoCs
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| Feb 28, 2011 | Synopsys DesignWare IP First to Support Final Release of PCI Express 3.0 Specification
Additional New DMA Engine and 256-bit Datapath Address Enterprise Computing Performance Requirements
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| Feb 22, 2011 | Synopsys Announces Immediate Availability of Silicon-Proven DesignWare Data Converter IP in SMIC 65-nm LL Process Technology
Family of High-Performance, Low Power Data Converter IP Eases Integration Effort and Lowers Risk for Wireless Communications and Digital TV SoCs
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