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Dec 09, 2014Synopsys' New LPDDR4 Verification IP Accelerates Verification Closure for High-Performance Low Power Designs
Native SystemVerilog-based Memory VIP Portfolio Expanded to Support JEDEC LPDDR4 with Built-in Coverage, Verification Plan and Protocol-aware Debug

Nov 19, 2014Synopsys Expands IP Accelerated Initiative with New DesignWare IP Prototyping Kits for 10 Interface Protocols
IP Prototyping Kits Enable Designers to Accelerate Prototyping, Software Development and Integration of IP into SoCs

Nov 11, 2014Nitero Achieves First-Pass Silicon Success for Industry's First Mobile 60GHz SoC Using Synopsys DesignWare IP for PCI Express and Tools
High-Quality DesignWare IP, Verification IP and Galaxy Design Platform Tools Deliver Lower Power, Smaller Area and Faster Time-to-Market for Wi-Fi Networking SoC

Nov 06, 2014KYOCERA Document Solutions Uses Synopsys’ Application-Specific Instruction-Set Processor Tool to Accelerate Design of High-Performance Image Processing DSP
Processor Designer Tool Enables KYOCERA Design Team to Reduce Overall Project Schedule by Nine Months

Oct 30, 2014Synopsys Announces Availability of DesignWare Non-Volatile Memory IP for TowerJazz 180-nm Process Technology
Silicon-Proven, Reprogrammable NVM IP Delivers Smallest Area for Calibration and Trimming Applications

Oct 29, 2014Synopsys' New DesignWare Sensor and Control IP Subsystem Delivers Ultra Low Power Sensor and Control Processing for SoCs
Integrated IP Subsystem, Including ARC EM DSP Processors, Floating Point Unit and Control Peripherals, Improves Performance, Energy Consumption and Design Flexibility

Oct 28, 2014Synopsys' New USB 3.1 IP Solution Enables 10 Gbps Data Transfer Speeds for Storage, Digital Office and Mobile Applications
Industry-First Solution Includes DesignWare USB 3.1 Controller, IP Virtual Development Kit and Verification IP

Oct 21, 2014Synopsys STAR Memory System Multi-Memory Bus Processor Enables 10 Percent Die Size Reduction for Marvell SoC
New Multi-Memory Bus Processor Cuts Test Logic in Half While Maintaining High Performance for Networking SoC

Oct 20, 2014Synopsys Introduces Industry's First On-Chip Memory Test and Repair Solution for Embedded Flash
DesignWare STAR Memory System for Embedded Flash Reduces Test Cost by 20 Percent and Enables In-Field Diagnostics for IoT and Automotive SoCs

Oct 14, 2014New DesignWare ARC HS38 Processor Doubles Performance for Embedded Linux Applications
Successor to Popular ARC 770D Core Delivers Significant Performance Increase, Support for 40-bit Physical Addresses and L2 Cache

Oct 08, 2014TSMC Selects Synopsys as "2014 Partner of the Year" for Interface IP and Joint Development of 16-nanometer FinFET Plus Design Infrastructure


Oct 07, 2014Synopsys Releases Verification IP for Mobile PCIe Technology
Native SystemVerilog-based VIP for PCI Express architecture now supports M-PCIe technology, with built-in coverage, verification plan and protocol-aware debug

Sep 18, 2014AMD and Synopsys Expand IP Partnership


Sep 18, 2014Leadcore Achieves First-Pass Silicon Success with DesignWare MIPI IP in Smartphone Application Processor SoC
High-Quality, Silicon-Proven IP Accelerates Project Schedule by Four Months in Highly Competitive Mobile Market

Sep 17, 2014Synopsys' New MIPI C-PHY Verification IP Accelerates Adoption of MIPI Alliance's Physical Layer Specifications
Native SystemVerilog-based MIPI C-PHY Verification IP Broadens Synopsys' VIP Portfolio Enabling Verification of Full Family of MIPI Alliance PHY Options

Sep 17, 2014Synopsys' New DesignWare MIPI D-PHY Cuts Area and Power by 50 Percent
Industry-First Support for MIPI D-PHY v1.2 Specification Increases Performance to 2.5 Gbps While Lowering Cost for Image Sensor and Display Applications

Sep 10, 2014Wipro Accelerates SoC Verification with Synopsys Verification IP Portfolio
Native SystemVerilog-based VIP Used in Advanced Testbench Methodology Environment to Address SoC Verification Challenges

Sep 04, 2014Synopsys Showcases DesignWare IP Solutions for USB 3.1 and PCI Express 4.0 at Intel Developer Forum 2014


Aug 21, 2014Synopsys DesignWare USB 3.0 IP Shipped in More Than 100 Million Production SoCs
Use of Silicon-Proven DesignWare USB IP by More than 60 Companies Demonstrates High Quality and Low Integration Risk

Jul 15, 2014Emulex Accelerates Verification Closure with Synopsys Verification IP for Ethernet
Native SystemVerilog Ethernet 1G/10G/40G/100G VIP now includes UNH compliance source-code test suite

Jul 08, 2014Synopsys Cuts Area of DesignWare NVM IP for Automotive Grade 0 Applications by 75 Percent
New Trim NVM IP Leverages Faster Programming Times to Reduce NVM Test Time by 3X Without Compromising AEC-Q100 Quality

Jul 08, 2014Synopsys Expands Verification IP Portfolio with Compliance Test Suites
Protocol test suites in SystemVerilog source code accelerate compliance testing of Ethernet, USB, PCI Express, ARM AMBA AXI and MIPI CSI-2 protocols

Jun 24, 2014Synopsys Announces Immediate Availability of Broad Portfolio of IP for TSMC 28HPC Process
Production-Ready DesignWare IP for TSMC 28HPC Process Enables Designers to Reduce Power Consumption and Area for Mobile and Ultra Low-Power IoT Designs

Jun 03, 2014Synopsys Expands Verification IP Portfolio with Memory Models
DDR and LPDDR Verification IP Now Broadly Available




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