DesignWare IP Subsystems 


As both hardware and software complexity increases, more advanced and integrated IP solutions are required to help designers meet their aggressive project schedules without compromising quality. Synopsys provides designers with a pre-verified DesignWare® Audio IP Subsystem and Sensor IP Subsystem consisting of hardware and software solutions that deliver complete, complex functions that are ready to integrate into an SoC.

By pre-integrating specific IP blocks together with an efficient processor and software in a single subsystem, Synopsys gives designers configurable, SoC-ready subsystem solutions that can significantly reduce their design and integration effort, lower design risk and accelerate time-to-market.

PDF DesignWare Audio IP Subsystem Datasheet
PDF DesignWare Sensor IP Subsystem Datasheet
PDF The Rise of SIP Subsystems: What is the Value to Silicon Architects and SoC Designers (White Paper)


Complete, configurable audio IP subsystem, supporting 2.0 to 7.1 audio streams with 24-bit precision to meet requirements of a range of audio applications such as digital TVs, set-top-boxes and portable audio devices

Complete, configurable sensor IP subsystem optimized to process data from digital to analog sensors, offloading the host processor and enabling more power-efficient processing of sensor data

  • Integrated, pre-verified hardware and software IP subsystem consisting of a power- and area-efficient ARC® 32-bit processor, digital and analog interfaces, hardware accelerators, software library of DSP functions and I/O drivers
  • Highly configurable with tightly integrated peripherals and dedicated hardware maximize sensor processing efficiency
  • More than ten configurable hardware accelerators reduce memory footprint and decrease power consumption by a factor of 10 compared to equivalent discrete component implementations
  • Extensive library of off-the-shelf software DSP functions, including mathematical, filtering, matrix/vector and decimation/interpolation, speeds application software development
  • Implementations as small as 0.01mm2, consuming less than 4uW/MHz in a 28-nm process

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