Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
Gervais Fong, Product Marketing Manager, Synopsys Eric Huang, Product Marketing Manager, Synopsys

Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Graham Allan, Senior Product Manager, Synopsys

This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths: Guidelines that help achieve functional correctness and intended behavior of arithmetic expressions in RTL code. Guidelines that help datapath synthesis to achieve best possible QoR (Quality of Results).
Reto Zimmermann – Synopsys