Verification IP and Verification Methodology Manual (VMM) for SystemVerilog
The Verification Methodology Manual for SystemVerilog, co-authored by Synopsys and ARM, defines a coverage-driven, constrained random methodology that speeds time to reach coverage goals. DesignWare Verification IP provides extensive support for the VMM and includes scenario generators and transactors to significantly reduce testbench development time.

Verification IP and Native Testbench
For high performance verification, DesignWare Verification IP supports VCS Native Testbench (NTB) technology. VCS compiles the Verification IP natively to provide up to five times faster runtime performance. DesignWare Verification IP also supports Pioneer NTB, Synopsys testbench automation tool, to give high performance in ModelSim and NC-Sim simulation environments.

VCS Verification Library
The VCS Verification includes all of the DesignWare standards-based verification IP and Star IP design views. The broad portfolio of the verification IP in the VCS Verification Library integrates easily into SystemVerilog, Verilog, OpenVera and VHDL testbenches to generate and respond to bus traffic, check for protocol violations, and generate coverage reports. The VCS Verification Library supports the Verification Methodology Manual (VMM) for SystemVerilog using Synopsys' Reference Verification Methodology (RVM).

Key Benefits

Broadest verification IP portfolio in the industry

Delivers 5X simulation performance improvement with VCS

Supports proven verification methodology for SystemVerilog

Includes example testbenches to accelerate learning and speed testbench development

The DesignWare Verification IP Alliance program gives designers access to a broader range of VMM-enabled verification IP, which complements DesignWare Verification IP. Members of the Alliance program have been pre-qualified by Synopsys for their extensive experience in verification methodology, VMM and verification IP development. The Verification IP included in the Alliance program is available from the member companies. It is developed using the same guidelines as the DesignWare Verification IP to help ensure that a consistent use model is delivered to designers.

The current Alliance members include:

eInfochips Inc. is a provider of product development solutions and services to Semiconductor companies worldwide. eInfochips’ goal is to help companies address their challenges related to IP integration, verification and technology migration in order to reduce the time to market for their products. eInfochips expertise spans design, verification, HVL-based verification methodology, system validation, and industry standard Verification IP development.

NoBug is an expert digital design verification company that masters a full range of technologies (functional, formal and assertion-based) with a variety of tools and languages (SystemVerilog,RuleBase, Vera, Verilog-PLI/C). NoBug’s goal is to establish strategic customer/client relationships designed to help deliver a customer-centric, total solutions approach to solving problems, developing business opportunities and creating sustainable advantage for their customers.