Webinars 

How Reliable is Your FPGA Design? Tips for Building-in High Reliability and Functional Safety
In this webinar, you will learn how to automatically “build-in” high reliability with Synopsys Synplify Premier FPGA design tools.
Paul Owens, Technical Marketing Manager, Synopsys, Inc.
Sep 27, 2016
 
Speed Software Development and IP Validation for ARMv8-based SoCs with Juno ARM Development Platform
This webinar introduces the new HAPS adaptor to connect a Juno ARM® Development Platform (ADP) to a Synopsys HAPS® Prototyping System or DesignWare® IP Prototyping Kit .
Achim Nohl, Technical Marketing Manager, Synopsys; Hugo Neto, Technical Marketing Manager, Synopsys
Jul 21, 2016
 
Accelerate your FPGA Design Schedules with Synplify Premier
This webinar will detail how Synplify Premier supports each design phase through improvements in automation, constraint setup, technologies for the best timing QoR and debugger information.
Paul Owens, Senior Corporate Applications Engineer, Synopsys
Mar 23, 2016
 
How Flexible Debug Can Speed Physical Prototype Bring-Up and Software Development
This webinar will provide an overview of the wide spectrum of critical debug techniques for efficient FPGA-based prototype bring-up, embedded software development and hardware/software integration.
Achim Nohl, Technical Marketing Manager, Synopsys
Mar 02, 2016
 
Software is eating the World: End-to-End Prototyping to the Rescue
Co-hosted by Chris Rommel of VDC, this webinar will explore the value between prototyping methods and their benefits for enabling early architecture exploration, software development, hardware-software integration and system validation.
Tom De Schutter, Senior Product Marketing Manager, Synopsys; Chris Rommel, Executive Vice President, IoT& Embedded Technology, VDC
Nov 04, 2015
 
A High Performance and Affordable Way to Validate SoC and ASIC Designs
This webinar will introduce Synopsys' HAPS®-80 Series of FPGA-based prototyping systems, which have been designed to deliver maximum system performance and support for up to 1.6 billion ASIC gates.
Neil Songcuan, Senior Product Marketing Manager, Synopsys
Sep 30, 2015
 
Optimize DDR Memory Subsystem Efficiency With Synopsys Platform Architect
The Synopsys DesignWare Enhanced Universal DDR Memory Controller (uMCTL2) provides sophisticated features to optimize DDR memory efficiency for your application while managing quality of service for individual transaction streams. The tools and techniques demonstrated in this session have been shown to produce a more optimal DDR controller configuration, improving memory bandwidth while avoiding the risk of over-design. A case study illustration will show how you can optimize the address mapping, clock frequency, and quality of service configuration for your SoC application to increase DDR memory efficiency up to 20%.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys, Inc.; Tim Kogel, Solution Architect, Synopsys, Inc.
Jun 05, 2015
 
Configure, Integrate & Prototype IP in Minutes
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits , Synopsys
Jun 03, 2015
 
Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015
 


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