DesignWare Embedded Memories, Test and Logic Libraries 


Today’s demanding applications require silicon technologies to take up less space while delivering more functionality with lower power. In addition, the combination of shrinking process technologies and increasing design complexity makes it more difficult to achieve high yield, so a robust memory repair solution is critical for achieving superior test quality and high manufacturing yield.

Synopsys' DesignWare® Embedded Memory and Logic Library portfolio offers the largest selection of silicon-proven, low-risk, easy-to-integrate memory and logic IP available today. The High Performance Core (HPC) Design Kit contains a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three. In addition, the DesignWare STAR Memory System® provides an integrated built-in self-test (BIST) and repair solution that improves test quality and manufacturing yield, while the DesignWare STAR Hierarchical System automates hierarchical testing for analog/mixed-signal IP, digital logic blocks and interface IP on an SoC. Synopsys’ comprehensive solution of embedded memories, test and logic libraries gives you everything you need to implement a full SoC and achieve the best combination of power, performance, area and yield.

Memories, Test and Logic Libraries


Synopsys, Realtek and UMC Collaborate on Industry's First Single-Chip Ultra High Definition Smart TV SoC
Realtek's Chip Achieves First-Pass Silicon Success Using Broad Portfolio of DesignWare Logic Libraries and Embedded Memories in UMC's 40-nm Process

Synopsys and CEVA Deliver Superior Performance, Power and Area for CEVA DSP Cores with DesignWare HPC Design
HPC Design Kit of Optimized Embedded Memories and Logic Libraries Yields 8 Percent Performance Improvement and 13 Percent Leakage Power Reduction with Smaller Area for CEVA-XC DSPs

Synopsys Announces DesignWare STAR Hierarchical System to Accelerate Silicon Testing of SoCs
Significantly Reduces Test Integration Time and Improves Test QoR for Hierarchical SoCs

Synopsys Announces Design Kit Optimized for All SoC Processor Cores
DesignWare HPC Design Kit Yields Superior Performance, Power and Area for CPU, GPU and DSP Cores

Synopsys Introduces Memory Test and Repair Solution for Designs at 20 Nanometers and Below
STAR Memory System's New Architecture and Test Algorithms Reduce Test Area up to 30 percent and Increase Coverage for New Memory Defects

Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
Advanced Memory and Logic IP Enable Designers to Optimize 28-nm SoCs for Both Maximum Performance and Low Power Consumption

Synopsys’ DesignWare STAR Memory System Shipped in 1 Billion Chips
Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories

White Paper: CPU, GPU and DSP Core Optimization for High Performance and Low Power
Each new process technology provides opportunities to optimize CPU, GPU and DSP processor core implementations to achieve better performance, power and area (PPA) results. This paper provides guidelines for establishing core design targets, selecting a design kit of standard cells and embedded memories and using implementation best practices to achieve PPA targets most efficiently.

Article: One Design Kit?
Instead of each processor having its own design kit, what if there was a single design flow, integrated with a set of libraries and memories that could be used across an entire SoC for a specific foundry process, that addressed the diverse of requirements of CPUs, GPUs, DSPs and general SoC blocks?

Article: Optimizing High-Performance CPUs, GPUs and DSPs? Use Logic and Memory IP – Part I
In Part I of this two-article series we described how the combination of logic libraries and embedded memories within an EDA design flow can be used to optimize area in CPU, GPU or DSP cores.

Article: Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP—Part II
In Part II we explore methods by which logic libraries and embedded memories can be used to optimize performance and power consumption in these processor cores.

Article: Embedded Memory Test & Repair at 20-nm Nodes and Below
This article provides an overview of the newly released DesignWare® STAR Memory System® 5 to specifically address the challenges of designs on 20 nm and below.

Article: High-Performance Logic Libraries for Core Hardening
This article discusses the best technology and techniques for hardening CPU cores. These are fundamental principles that apply to CPU cores that are targeted to achieving the optimal PPA from the silicon process. You will learn proven best practices and solutions that can be immediately applied to your core optimization project to achieve best results.

Article: Embedded Memory Test and Repair Optimizes SoC Yields
As process technologies continue to shrink while memory size and design complexity grow, designers are faced with new memory defects and failure mechanisms in their designs, which ultimately result in lower yield. New and emerging design challenges make it critical for embedded memory test and repair solutions to keep up with technology advances in order to consistently provide superior test quality and yield optimization.

Article: Selecting Standard Cell and Memory IP to Meet Chip Goals
Designers must make practical trade-offs in performance, power consumption and die area, or PPA, in virtually every SoC implementation today. This article explains how the Synopsys' DesignWare® Duet Packages of Embedded Memories and Logic Libraries provide design teams all of the fundamental IP elements needed to strike the best combination of performance, power and area in their system-on-chip (SoC) implementations.

Success Story: PLX First to Market with PCI Express Gen 3 Switch using DesignWare Embedded Memory IP
"After qualifying several vendors, we found Synopsys' silicon-proven DesignWare Embedded Memory portfolio offered the broadest range of compilers with an array of options to meet our varied design requirements. The combination of small area, high performance and advanced power management capabilities made selecting Synopsys an easy choice."
Syed Ahmed, Senior Director of Physical Design, PLX Technology

Video: Introducing the DesignWare HPC Design Kit
Learn how Synopsys' DesignWare HPC (High Performance Core) Design Kit, a single package containing high-speed and high-density memory instances and standard cell libraries, allow designers to optimize all their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power, or an optimum balance of the three. Hear about the latest results achieved through Synopsys' collaboration with Imagination on the Imagination PowerVR™ Series6 GPU core.

Webinar: Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/ power/ area targets, and how choosing the correct IP/ methodology avoids physical design bottlenecks.

Webinar: Reduce SoC Test Cost and Cut Weeks off Test Integration with Hierarchical Testing of all IP on a SoC
In this webinar we will describe how the DesignWare STAR Hierarchical System leverages IP and logic block-level test and accelerates SoC testing by enabling faster design closure.

Video: Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair

Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs
Learn about ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets.

Webinar: Optimizing Power in High-Performance SoCs using Multiple Voltage/VT/Channel Length Libraries
Learn ways to maximize system performance and minimize cost while slashing power budgets of SoC blocks operating at different clock speeds.

Webinar: A Large Capacity SRAM Alternative to Embedded DRAM
Learn how combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM.

Synopsys provides designers with the industry's broadest portfolio of high-speed, high-density and low-power embedded memories and logic libraries. The DesignWare Memory Compiler and Logic IP solutions are silicon-proven with billions of units shipping in volume production, enabling you to lower risk and speed time-to-market.

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Select the best IP solution for your design with the Memory and Logic IP Selector Tool.

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