New STAR Memory System 5 

Hierarchical memory test and repair capabilities for 20 nanometers and below  
The latest version of the DesignWare® STAR Memory System® has advanced memory test and repair algorithms to address new memory defects, including process variation faults and resistive faults, that are more prevalent at 20-nanometer (nm) and below (FinFET) technologies. The new performance-and area-optimized hierarchical architecture reduces test and repair area by 30% compared with the previous generation and hierarchical implementation and validation capabilities accelerate the design cycle by allowing incremental generation, integration and verification of test and repair IP at various design hierarchy levels.
With the new version, customers can achieve:
  • Highest quality test
    • At-speed memory defect coverage with minimum test time at all technology nodes including 20nm and below
    • Silicon-proven solution ensures low DPPM and low risk
  • High yield
    • Efficient power-aware, on-chip repair across multiple operating corners provides maximum repair with available resources
    • Faster repair recovery for low-power designs
  • Increased design productivity
    • Automated hierarchical implementation and validation accelerates the design cycle
    • Optimized architecture and advanced capabilities provides best performance, power, area and memory test QoR
  • Superior diagnostics
    • Advanced failures diagnostic capabilities such as physical failed bitmaps, XY coordinate identification and fault classification of failures reduces time-to-yield and time-to-volume

Find out more…
Article: Embedded Memory Test and Repair Optimizes SoC Yields
Article: 20nm Test Demands New Design-for-Test and Diagnostic Strategies
STAR Memory System Datasheet
Press Release: Synopsys Introduces Memory Test and Repair Solution for Designs at 20 Nanometers and Below

New STAR Memory System
Figure 1: DesignWare STAR Memory System 5: Advanced test, repair and diagnostics for 20nm and below.

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