Article: Embedded Memory Test and Repair Optimizes SoC Yields
As process technologies continue to shrink while memory size and design complexity grow, designers are faced with new memory defects and failure mechanisms in their designs, which ultimately result in lower yield. New and emerging design challenges make it critical for embedded memory test and repair solutions to keep up with technology advances in order to consistently provide superior test quality and yield optimization.
Article: Selecting Standard Cell and Memory IP to Meet Chip Goals
Designers must make practical trade-offs in performance, power consumption and die area, or PPA, in virtually every SoC implementation today. This article explains how the Synopsys’ DesignWare® Duet Packages of Embedded Memories and Logic Libraries provide design teams all of the fundamental IP elements needed to strike the best combination of performance, power and area in their system-on-chip (SoC) implementations.
Success Story: PLX First to Market with PCI Express Gen 3 Switch using DesignWare Embedded Memory IP
“After qualifying several vendors, we found Synopsys’ silicon-proven DesignWare Embedded Memory portfolio offered the broadest range of compilers with an array of options to meet our varied design requirements. The combination of small area, high performance and advanced power management capabilities made selecting Synopsys an easy choice.”
Syed Ahmed, Senior Director of Physical Design, PLX Technology
Synopsys Announces DesignWare Embedded Memories and Logic Libraries for TSMC 28-nanometer Processes
Advanced Memory and Logic IP Enable Designers to Optimize 28-nm SoCs for Both Maximum Performance and Low Power Consumption
Synopsys’ DesignWare STAR Memory System Shipped in 1 Billion Chips
Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories
- A Large Capacity SRAM Alternative to Embedded DRAM
In this webinar, learn:
- How combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM
- Ways to improve system performance when dealing with spatially disparate accesses in large memory
- Optimizing Power in High-Performance SoCs using Multiple Voltage/VT/Channel Length Libraries
In this webinar, learn:
- How combining innovative power management techniques using multiple VTs/channel lengths in different SoC logic blocks delivers the optimal tradeoff in SoC watts per gigahertz
- Ways to maximize system performance and minimize cost while slashing power budgets of SoC blocks operating at different clock speeds
- Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies
In this webinar, learn:
- About the technical trends and challenges associated with embedded test, repair and diagnostics in today's designs
- About the trade-offs and design impact of various solutions
- How Synopsys' DesignWare STAR Memory System® can meet your embedded test, repair and diagnostics needs
DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair
This demonstration features the post-silicon interactive automation capabilities of the DesignWare' STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Synopsys provides designers with the industry's broadest portfolio of high-speed, high-density and low-power embedded memories and logic libraries. The DesignWare Memory Compiler and Logic IP solutions are silicon-proven with billions of units shipping in volume production, enabling you to lower risk and speed time-to-market.
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