DesignWare Embedded Memories and Logic Libraries 

 

Synopsys provides a broad portfolio of high-quality, silicon-proven embedded memory and logic library solutions, enabling system-on-chip (SoC) designers to lower integration risk and speed time-to-market.

The DesignWare® Duet Packages of Embedded Memories and Logic Libraries include memory compilers, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs that enable designers to achieve the maximum performance with the lowest possible power consumption for their specific application. The High Performance Core (HPC) Design Kit contains a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of all three. In addition, the DesignWare STAR Memory System® provides an integrated built-in self-test (BIST) and repair solution that improves test quality and manufacturing yield, while the DesignWare STAR Hierarchical System automates hierarchical testing for analog/mixed-signal IP, digital logic blocks and interface IP on an SoC.

Synopsys also provides a comprehensive family of multiple-time programmable (MTP) and few-time programmable (FTP) non-volatile memory (NVM) IP in standard CMOS process technologies.

  • Products
 
  • Embedded Memories
  • Embedded SRAMs with test and repair and non-volatile memories (NVMs) 

Memory Compilers
DesignWare Memory Compilers are optimized for high performance and high density with advanced power management features. Integrated STAR Memory System for detection and repair of manufacturing faults improves yield.
The memory compilers are also a part of the DesignWare Duet Packages and HPC Design Kit.


Non-Volatile Memory
Multiple time programmable (MTP) and few time programmable (FTP) embedded non-volatile memories for a broad range of process technologies.


STAR Memory System
The DesignWare STAR Memory System is a comprehensive, integrated test, repair and diagnostic solution that supports repairable and non-repairable embedded memories across any foundry or process node


STAR Hierarchical System
The DesignWare STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs, including analog/mixed-signal IP, digital logic blocks and interface IP.

  • Logic Libraries
  • Logic libraries for a wide array of applications and process technologies 

Standard Cell Libraries
DesignWare Standard Cell Libraries provide high-speed (HS), high-density (HD) and ultra high-density (UHD) architectures to optimize circuits for performance, power and area tradeoffs.
The standard cell libraries are also a part of the DesignWare Duet Packages and HPC Design Kit.


Power Optimization Kits (POKs)
Minimizing power consumption while sustaining optimal performance and are available for DesignWare Logic Libraries at 65-nm and below


Engineering Change Order (ECO) Kits
The metal programmable cell libraries, available in high-speed and high-density architectures, are most beneficial to designers who are looking for a foundation for low-cost mask designs.

  • Duet Packages
  • Duet Embedded Memories and Logic Libraries and HPC Design Kit 

Duet
DesignWare Duet Packages include all the physical IP needed to achieve the best combination of speed, power, and area for your entire SoC.


High Performance Core (HPC) Design Kit
A suite of high-speed and high-density embedded memories and logic libraries deliver optimized performance, power and area on CPU, GPU, and DSP cores.



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