Processor Designer 

Automating the Design and Implementation of Application-Specific Processors (ASIP)   

Processor Designer dramatically accelerates the design of application-specific instruction-set processors (ASIP) through automated software development tools, RTL and ISS generation from a single, high-level specification. An ASIP might be a custom processor or a programmable accelerator. Custom processors are increasingly essential to support the convergence of multiple functionalities all on a single system-on-chip (SoC), addressing the need for programmability, power efficiency and performance. Demanding applications like audio, security, networking, baseband, control and industrial automation are ideal for ASIPs. Embedded vision is another key domain, with applications such as advanced driver assistance systems, gesture control and augmented reality calling for performance and power optimized processors.
PDF PROCESSOR DESIGNER DATASHEET (PDF)

 

With the constant drive towards more integrated devices that perform a variety of functions and support multiple standards, flexibility is becoming the buzzword of today’s design teams. These teams are tasked with developing products that can deal with growing performance demands, consume as little power as possible and can process parallel functions all while meeting time-to-market pressure. While enabling performance and low power, in a lot of cases fixed hardware blocks are inadequate because of their lack of flexibility, reusability and ability to deal with multiple modes and standards. For a lot of specific tasks standard processors have challenges of their own in terms of meeting the performance and power consumption requirements.

This is where application-specific processors (ASIPs), also referred to as custom processors are saving the day. Their unique ability to offer flexibility through software reprogrammability while limiting overhead makes them the ultimate trade-off between flexibility and power, performance and area. ASIPs have the added benefit that they reduce the verification effort by decoupling the hardware verification and the functional verification.

Processor Designer takes creation of custom processor to the next level by providing one formal input specification for ISS, software tools (assembler, linker, debugger and compiler) and RTL implementation model. The unique ASIP implementation flow of Processor Designer achieves quality results. Overall the benefits are clear - more flexibility to deal with today’s and future requirements, reduced verification effort and no compromises on power, area and performance. This not only results in faster time-to-market but ensures higher reuse between iterative designs.

Contact Synopsys and find out how you could benefit from ASIPs made easy.

Highlights
  • Integrated design environment for application-specific processors (ASIPs), be it custom processors or programmable accelerators
  • Slashes custom processor and programmable accelerator hardware design time by months
  • Eliminates months of engineer-effort for software tool development through the automated generation of assembler, linker, debugger and compiler
  • Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation
  • Software development environment enables application software development prior to silicon availability

Synopsys Processor Designer is an automated, application-specific processor (ASIP) design and optimization tool that slashes months from custom processor hardware design time. It also eliminates months of engineer-effort typically needed for the creation of application processor-specific software development tools. Processor Designer's high degree of automation enables design teams to focus on architecture exploration and application-specific processor development, rather than on consistency checking and verification of individual tools.

Processor Designer dramatically accelerates the design of ASIPs, which might be a custom processor or a programmable accelerator. Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP-specific and RISC-specific features as well as SIMD and VLIW architectures.

Processor Designer's generated software development environment enables the commencement of application software development prior to silicon availability, thus eradicating a common bottleneck in embedded system development.

What is Embedded Vision?

Embedded vision is about extracting meaning from visual input by using computer vision algorithms implemented on an embedded system. Fueled by increasing processing power of embedded devices and research in computer vision theory, embedded vision is moving into emerging high-volume consumer applications such as smart glasses, augmented reality, home surveillance, gaming systems, and automotive.

Learn more about the Embedded Vision Alliance. Resources for creating ‘machines that see’

Embedded Vision Development System

Reduce Development Time for Power and Performance Optimized Processors from Months to Weeks using Processor Designer and HAPS

Highlights
  • Design embedded vision processor, tailored to specific power and performance requirements
  • Explore and tune new processor architectures in hours instead of weeks
  • Reduce system bring-up time by months with pre-validated embedded vision reference flows for HAPS® FPGA-based prototypes

Synopsys' Embedded Vision Development System combines Synopsys' Processor Designer's unique capability to design application-specific processors (ASIPs) with Synopsys' HAPS FPGA prototyping system that allows for rapid hardware/software validation through the integration of other digital IP an interfacing with real-world I/O such as cameras and memory.

Embedded vision systems call for the three P's:
  • Performance: real-time execution of very complex algorithms, often exceeding 10 billion operations per second
  • Power efficiency: embedded systems are power-sensitive, either because they are battery operated, or can't afford additional power supplies or cooling
  • Programmability: algorithms are evolving, and devices need to be upgraded and tuned while deployed in the field

While CPU and GPU address programmability, they often don't meet the power/performance specification. On the other end, dedicated logic can jointly optimize power and performance, but lacks programmability. The three P's call for the deployment of application-specific processor (ASIPs), featuring optimized instruction-sets and memory architectures tailored to the application.

The Embedded Vision Development System includes pre-verified design examples to help designers quickly implement and prototype an ASIP optimized to meet their specific SoC objectives for power consumption and performance. The pre-configured HAPS setup includes the support of I/O interfaces and external memory cards, saving weeks of setup time. In consequence, designers can concentrate on their processor and SoC architecture as the system provides a highly efficient way to refine and validate various architectures.

In addition to reference examples, the Embedded Vision Development System provides a base-RISC processor in source code that is fully modifiable. It comes with an extendable C/C++ compiler as well as C/C++ runtime libraries. The OpenCV function library has been ported to run on this processor/compiler setup. The execution of the compiled code with the automatically-generated instruction-set simulator (ISS) is easy to profile, clearly identifying performance intensive parts of the application, which can be accelerated by changes in the processor architecture, including memory access, register configuration and instruction set. Unlike configurable processors that rely on a fixed pipeline and register structure, this methodology has no limitations for achieving the most power- and performance-optimized custom architecture. Using the automatically generated software tools, designers easily recompile and simulate the C/C++ program until design goals are attained.

Watch the video.

Embedded Vision Processor
Embedded Vision Processor Design Made Easy using Processor Designer and HAPS FPGA-based Prototyping

The key to Processor Designer's automation is its Language for Instruction Set Architectures, LISA 2.0. In contrast to SystemC, which has been developed for efficient specification of systems, LISA 2.0 is a processor description language that incorporates all necessary processor-specific components such as register files, pipelines, pins, memory and caches, and instructions. It enables the efficient creation of a single golden processor specification as the source for the automatic generation of the instruction set simulator (ISS) and the complete suite of software development tools, like Assembler, Linker, Archiver and C-Compiler, and synthesizable RTL code. The development tools, together with the extensive profiling capabilities of the debugger, enable rapid analysis and exploration of the application-specific processor's instruction set architecture to determine the optimal instruction set for the target application domain. Processor Designer enables the designer to optimize instruction set design, processor micro-architecture and memory sub-systems, including caches.

Processor Designer's use of a single high-level processor specification ensures the consistency of the ISS, software development tools and RTL implementation, eliminating the verification and debug effort necessitated by multiple, independently-created models.

Operating at a high level of abstraction, Processor Designer not only eliminates the time and cost inherent in HDL-based processor design and manual tool development, but also enables hardware and software designers to customize the instruction set to their needs.

Custom Processor Development CoStart
The CoStart program is intended to be a vehicle to rapidly get up to speed using Synopsys Processor Designer for custom processor development. The program contains an intense knowledge transfer, while assisting in the project planning, model development and optimization, subsystem integration, and the fine tuning of the end results such as the RTL implementation or the software tools.

Project Objectives
  • Project, methodology and tool flow coaching in order to produce better results in a shorter time
  • Sharing user experience and raising the knowledge and expertise for processor modeling using LISA to successfully meet design goals
  • Leveraging the PD Starter Kit providing design data and documentation to quickly get up to speed with Processor Designer and LISA
  • Avoiding the risk of not achieving goals by a misinterpretation of the recommended design and modeling flow
  • Maximizing the value of the Synopsys value links to software development (Virtual Prototyping and FPGA-Based Prototyping), implementation (Design Compiler) and verification (VCS)


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