|Designing Application-Specific Processors for Wireless Baseband SoCs|
Traditional architectures for wireless baseband applications are no longer adequate for next-generation modem standards. Supporting multiple, evolving standards in a single modem is only possible by using SDR techniques, which place increasing demands on performance and power consumption on the SoC. ASIP architectures enable full customization of a processor, which allows design teams to better optimize their design’s wireless baseband SoCs. This white paper describes how tool-based ASIP design methodologies automate the generation of the software tool chain, including an optimized software compiler, and the generation of RTL for ASIC and FPGA implementation, which enables rapid architecture exploration and trade-off analysis between performance, power and area.
Bo Wu, Technical Marketing Manager, Synopsys, Inc.
|Designing ASIPs in Multicore SoCs|
Modern SoCs integrate dozens of complex system functions, each requiring its own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of fixed hardware accelerators no longer suffices. Application-specific instruction-set processors (ASIPs) can offer the best balance for each system function, and thus form the basis of new generations of multicore SoCs. ASIP design requires tools and methodologies that enable fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification. Any ASIP design approach has to support a broad range of architectures, from small microprocessors, over DSP dominated cores, to VLIW and vector processors.
Gert Goossens, R&D Director; Dirk Lanneer, R&D Manager; Werner Geurts, CAE Manager; Johan Van Praet, R&D Manager, Synopsys
|Design of Embedded Vision Processors|
In this paper, we discuss how Programmable Accelerators or ASIPs (Application Specific Instruction-set Processors) can help meet these challenges and introduce a simple and efficient ASIP design methodology using Synopsys Embedded Vision Development System. Taking the example of Canny Edge detection with an initial C/C++ implementation in the OpenCV library, we demonstrate how a basic RISC processor can be specialized for this vision application and achieve the power-performance balance for implementation on embedded devices.
Bo Wu, Ph.D., Technical Marketing Manager, Synopsys Inc.
|Custom Processors: A Better Way of Dealing with Design Changes|
This white paper provides you with the understanding of how custom processors offer the flexibility needed to deal with multiple standards, multiple modes and late design changes as well as help minimize verification effort. By means of specialization, they also offer an attractive trade-off between power, performance and area. This makes them ideal for use in a wide variety of applications including video, audio, security, networking, baseband, control and industrial automation applications.
Achim Nohl, Synopsys Inc. and Tom De Schutter, Synopsys Inc.