IP Designer 

 

Finding the right balance between efficiency and flexibility requires the ability to quickly evaluate alternative architectures. IP Designer™ offers a complete retargetable tool-suite for exactly this purpose.

IP Designer

With IP Designer, designers can define their ASIP architecture in the nML language. Automatically the IP Designer tools will work for this newly specified ASIP.

nML is a high-level definition language to describe a processor architecture and instruction set (ISA). nML offers designers the abstraction level of a programmer's manual of a processor.

IP Designer consists of the following retargetable tools:
  • A software compiler that maps C application programs into highly optimized machine code for the ASIP. This retargetable C compiler can cope well with architectural peculiarities of DSP cores. It supports instruction-level and data-level parallelism, deeply pipelined instructions, specialized arithmetic functions, custom data-types, specialized address generation units, heterogeneous register structures, and various degrees of instruction encoding (ranging from VLIW to highly encoded instruction sets). It produces machine code in the Elf/Dwarf object file format.

  • A linker that builds an executable file from separately compiled Elf/Dwarf object files for different C functions.

  • An assembler and disassembler that translates machine code from assembly into binary format and back.

  • An instruction-set simulator (ISS) and graphical debugger generator. The ISS offers bit-accurate execution of machine code, both at cycle-accurate and instruction-accurate level. Through a co-simulation interface, the ISS can easily be coupled to other simulators (e.g. co-simulation with an RTL model or with other ISSs, or integration in a SystemC or virtual platform model). It supports C source-level debugging based on Elf/Dwarf executable files. Its graphical debugger can also connect to the processor hardware to support on-chip debugging. The tool produces execution profiles to drive the optimization of the ASIP architecture and of the application software.

  • An RTL generator that translates the nML processor description into synthesizable register transfer language (RTL) hardware modell. A JTAG interface and a debug controller can optionally be generated, to support on-chip debugging.

  • A test program generator that generates processor-specific assembly test programs.

  • A graphical integrated development environment that integrates all the above tools.

Click on image to enlarge
Development perspective in ChessDE, showing compilation of an MPEG4 motion estimation function on an ASIP
Development perspective in IP Designer's development view, showing compilation
of an MPEG4 motion estimation function on an ASIP



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