IP Designer, IP Programmer and MP Designer  


For applications requiring highly specialized processing, application-specific instruction-set processors (ASIPs) deliver greater computational efficiencies than general purpose processors and more flexibility than fixed-function RTL designs. IP Designer, IP Programmer and MP Designer, formerly from Target Compiler Technologies, are ideal for creating ASIPs, which might be custom processors or programmable hardware accelerators that serve in next-generation SoCs, particularly where re-programmability provides a key competitive advantage. These tools enable designers to:

  • Create customized processing elements that are programmable in C
  • Adjust performance-sensitive algorithms without requiring silicon respins
  • Differentiate products using their own proprietary algorithmic IP
  • Reduce schedule risk and improve time-to-market with proven, highly automated tools



Complete retargetable tool suite to evaluate architectures for the optimal balance between efficiency and flexibility

Commercial-quality software development kits, including optimized C-compiler and high-performance simulation model

Complete tool-suite for heterogeneous multicore systems-on-chips, supporting key design tasks such as C code parallelization and platform generation

Support services to quickly model the appropriate ASIP architecture in nML for use with IP Designer and IP Programmer

What is nML?

nML is the key to quickly defining the right ASIP architecture for your requirements.

nML is a hierarchical and highly structured architecture description language that is used to represent ASIP designs at the abstraction level of a programmer's manual. It is used to model an ASIP architecture in a concise way, defining both the structural characteristics of the design as well as the instruction set architecture. nML has been carefully designed to contain the right amount of hardware knowledge to:

  • Enable rapid development and exploration of architectural alternatives.
  • Automatically generate highly efficient hardware designs (in the form of synthesizable RTL).
  • Assure that IP Designer's retargetable C compiler has sufficient information to yield optimally scheduled code for critical regions.
  • Enable generation of fast, yet cycle-accurate instruction-set simulators and simulation models.

nML models contain two basic parts.

The first part is a structural definition that accurately captures the datapath architecture of the ASIP, including all functional units, register files, memories, IO ports, and specialized registers, and the interconnection of these elements for data movement.

The second part is a definition of the instruction-set architecture (ISA) including the encoding and behaviors of each instruction. The second part is a hierarchical, grammar-based definition. Due to the broad architectural scope of nML, ASIP architectures for a wide variety of application areas can be defined. Examples application domains include:

  • Wireless and wireline communications (e.g., LTE modems)
  • Video and multimedia processing (including HD)
  • Audio (mobile and otherwise)
  • Medical and wearable devices
  • Automotive
  • Network processing

"The speed at which we can turn out a custom core using IP Designer still astonishes me. The tools also point out places to optimize your nML, instruction encoding, pipelining, etc."

-Benton Watson, Sound Design Technologies, Ottawa, Canada

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