Co-Design & Simulation 


Co-Design with Unique Modeling and Simulation Products
How much of your software development team's time is spent waiting for FPGA boards or for access to RTL simulators?

Advances in co-design and simulation have created more opportunities for first-pass success because now developers can simulate the entire system on a host PC prior to tape-out. DesignWare ARC offers a variety of simulation products encompassing the entire scope from automatically generated cycle accurate simulators to fast, functional instruction set simulators.

To enable SW development in an full SoC context DesignWare ARC provides a methodology package that allows virtualisation of the SW visible SoC components, such as peripheral registers, memories and interrupts. For further information contact your local DesignWare ARC representative.
Reduce Time to Market and Minimize Risk

  • Parallelize hardware and software development
  • Quickly iterate through multiple system configurations to determine the best options for your requirements
  • Increase the number of develop/debug/optimize cycles to ensure your product meets your requirements
Differentiate to Keep Competitive Edge

  • Add more features or respond to late feature requests with the schedule time gained
  • Prototype earlier in the development cycle to influence prospects and customers
  • Make your solution easier for your customers to integrate

DesignWare ARC offers a broad suite of simulation products that enable hardware / software co-design prior to silicon being available. Each product differs in its intended use model, speed, accuracy, and debug views.

  RTL xCAM Metaware ISS xISS Turbo
Use model Hardware development DesignWare ARC IP firmware and software development Software development Software development for large programs
Speed < 5 KHz 40 to 60 KHz 2 MHz 200+ MHz
Accuracy 100% Cycle Accurate 100% Cycle Accurate Instruction Accurate Instruction Accurate
Generated from ARChitect    
Creates C models for distribution        
Software "view" for debug  
Hardware "view" for debug
Interfaces with MetaWare Debugger
Imports into SystemC    
Metaware ISS for Quick SW Routine Development
Metware ISS is provided by default within the Metaware SW development toolkit. It enables easy development, test and debug of small SW components. The ISS provides additional capabilities that are not available on hardware, such as:

  • Set hardware watchpoints on memory and registers
  • Specify memory size and location
  • Stop execution on loads of a value
  • Trace instructions
  • View the most recently executed instructions
Within the Metaware ISS a cycle estimation component (CES) can be activated. It allows estimation of machine cycles when executing programs. The CES also includes a cache thrash analysis routine to point out cache thrashing. Simulation performance of the Metaware ISS goes up to ~2 MIPS.

xISS Turbo Fast ISS for Full Application Development
xISS enables fast development, software test and debug. DesignWare ARC  xISS and DesignWare ARC xISS Turbo are high-performance instruction-set level simulations that increase software development productivity at every stage of DesignWare ARC-Based product development. DesignWare ARC xISS Turbo uses advanced Just-in-Time Compiler technology to produce 200+ MIPS (millions of instructions per second) performance, while DesignWare ARC  xISS provides affordable yet advanced ISS capability at ~20 MIPS performance. Learn more >>

xCAM Generate for Instant Cycle Accurate Model Creation
With the addition of DesignWare ARC  xCAM, the ARChitect IP Configurator can automatically generate cycle accurate models of any customized DesignWare ARC  IP, allowing code to be tuned on the exact hardware configuration being considered. Executing at between 40kHz to 60kHz, xCAM models are available within minutes of a configuration being finalized, enabling a genuinely iterative design approach. xCAM models provide detailed cycle and "programmer's view" information for profiling and they easily import into SystemC co-development tools. Learn more >>


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