DesignWare ARC Options 


Synopsys offers a portfolio of separately licensable configurable options that enable DesignWare® ARC® processors to be optimized for a specific application or to add more processing capabilities. Options include Memory Protection Unit (MPU), Floating Point Unit (FPU), Real-Time Trace (RTT), safety enhancement package (SEP), XY Advanced DSP for the ARC 600 and 700 processors, µDMA controller, CryptoPack and enhanced security package, as well as ARConnect for multicore processor implementations.

The XY Advanced DSP option delivers full performance digital signal processing for ARC 600 processors. FPX and FPU floating point options add high-performance single- and double-precision math instructions to the ARC processors. Real-Time Trace options can be integrated into any SoC within the ARC configurable architecture. The SEP package is designed for use in ISO 26262 safety-compliant automotive applications. Security options available for ARC EM cores include cryptographic software algorithm accelerators and an enhanced security package, which enables designers to create a secure, tamper resistant environment that protects their systems and software from evolving security threats such as IP theft and intentional remote attacks. The ARC EM processor family also offers a µDMA controller option and ARConnect configurable hardware to facilitate multicore integration.


Division of address space into regions associated with specific attributes such as read, write, and execute prevents faulting instructions from completing

Adds high-performance single- and double-precision math instructions to dramatically accelerate computations

Enables rapid software debug with minimal increase in die size and no power consumption penalty

Enables designers to create a trusted, tamper resistant execution environment that protects their systems and software from security vulnerabilities

  • CryptoPack
  • Data encryption/decryption for area & power constrained devices more

Hardware extensions to accelerate common cryptographic software algorithms such as AES, SHA-256, RSA, DES and elliptic curve cryptography (ECC)

  • EM SEP
  • ARC EM with Safety Enhancement Package for automotive safety appsmore

For use in ISO 26262 embedded automotive safety-compliant applications, ARC EM cores with SEP integrate hardware safety features, which enable ASIL D compliance, into a highly efficient and compact processor.

Support for up to 16 programmable channels, two addressing modes, and five data transfer modes enables data movement to/from memory while the processor is in one of its eight sleep states

  • ARConnect
  • Inter-core communication for multicore integration more

Configurable hardware that manages inter-core communication, interrupt handling and debug to facilitate multicore integration

Adds the power of a true DSP engine to enable conventional and signal processing computation within a single unified architecture

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.

Power and cycle count reduction running sensor application software with APEX accelerators

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.

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