DesignWare ARC HS Processor Family 

Maximum Performance for Embedded Applications 

Synopsys' DesignWare® ARC® Processors are 32-bit CPUs that SoC designers can optimize for a wide range of uses, from deeply embedded to high-performance host applications.

The ARC HS Family includes the multicore-capable HS34 and HS36 processors. The HS34 is a high-performance cacheless processor, while the HS36 includes up to 64KB of instruction and data caches. Both processors are available in dual- and quad-core configurations. The HS processors are optimized to deliver maximum performance efficiency (DMIPS/mW and DMIPS/mm2), making them ideally suited for embedded applications with high-speed data and signal processing requirements. The high degree of configurability and extensible instruction set allows designers to tailor each HS processor instance on their SoC for the optimum balance of performance, power and area.

All ARC processor cores are supported by a robust ecosystem of software and hardware development tools, including the MetaWare Development Kit, a complete solution for developing, debugging, and optimizing embedded software on ARC processors, the MQX real-time operating system (RTOS) and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.

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  • ARC HS34
  • High-speed single-, dual- and quad-core cacheless processorsmore

 
Ideal for applications requiring deterministic response time such as solid state drives (SSDs), network-attached storage (NAS), home gateways, home networking, and mobile products.

  • ARC HS36
  • High-speed single-, dual- and quad-core processors with I and D cachesmore

 
Optimized for use in higher-end embedded applications such as digital cameras, digital TVs, set-top boxes, automobile infotainment and control systems, and networked devices.

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.



Power and cycle count reduction running sensor application software with APEX accelerators

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.



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