DesignWare ARC EM Processor Family 

Unrivaled Performance Efficiency for Your Embedded Application 

The DesignWare® ARC® EM Family of embedded processor cores is based on the scalable ARCv2 Instruction Set Architecture (ISA) and is optimized for performance efficiency (DMIPS/mW and DMIPS/mm2). The ARC EM family includes the EM4 (cacheless) and EM6 (instruction and data caches) processor cores, designed for use in power and area-sensitive embedded applications. They offer industry-leading performance efficiency of up to 1.77 DMIPS/MHz, with minimal area and power consumption.

The ARC EM DSP family, which includes the ARC EM5D and EM7D processors, are specifically designed for ultra low-power embedded DSP applications. The ARC EM DSP processors are based on the 32-bit RISC EM family, providing a balanced combination of efficient real-time control and DSP performance required for many ultra low-power, always-on, voice-activated and sensor processing applications. The ARC EM Safety Enhancement Package (SEP) processor is designed for use in ISO 26262 safety-compliant automotive applications.

The EM Processors are highly-configurable and extensible, enabling designers to implement each core with the optimum combination of performance, code density, area and power consumption for the specific task or application.

The EM Family of processor cores is supported by a robust ecosystem of software and hardware development tools, including an easy to use and low-cost ARC EM Starter Kit for early software development, the MQX real-time operating system (RTOS), and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program.

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  • ARC EM4
  • Ultra-compact and power-efficient cacheless 32-bit processor more

 
Ideal for embedded and deeply embedded applications such as sensors and actuators, memory cards, SSD controllers, 8- and 16-bit microcontroller replacement and battery-operated products.

  • ARC EM6
  • Ultra-compact and power-efficient 32-bit processor with I & D caches more

 
Optimized for use in embedded and deeply embedded applications that are power- and cost-sensitive such as memory cards, SSD controllers, power management, portable media players and other mobile devices.

  • ARC EM5D
  • Compact, power-efficient DSP-enhanced processor with I & D CCMsmore

 
DSP-enhanced processor with ICCMs & DCCMs delivers a perfect combination of efficient real-time control and DSP performance for ultra low-power, always-on IoT devices that process voice, audio and sensor data.

  • ARC EM7D
  • Power-efficient DSP-enhanced processor with I & D CCMs and cachesmore

 
DSP-enhanced processor with ICCMs, DCCMs and caches is optimized to deliver efficient real-time control and DSP performance for ultra low-power, always-on IoT devices that process voice, audio and sensor data.

  • ARC EM SEP
  • Safety Enhancement Package (SEP) Core for automotive safety applications more

 
For use in ISO 26262 embedded automotive safety-compliant applications, ARC EM SEP integrates hardware safety features, which enable ASIL D compliance, into a highly efficient and compact processor.

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.



Power and cycle count reduction running sensor application software with APEX accelerators

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.



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