The Synopsys' DesignWare® ARC™ EM Family of embedded processor cores is based on the next-generation ARCv2 Instruction Set Architecture (ISA). The ARCv2 architecture is a combined 16-/32-bit ISA that is implemented with a new scalable pipeline that enables the development of advanced RISC microprocessor cores with the optimum balance of performance, power consumption and size for a broad range of applications, giving designers a complete processor solution for their system-on-chip (SoC) designs.
The DesignWare ARC EM family includes the EM4 and EM6 processor cores, the first CPU cores built with the new ARCv2 ISA and pipeline. The DesignWare ARC EM4 and ARC EM6 are optimized for use in power-sensitive embedded and deeply embedded applications where high performance with minimum power consumption is essential. The cores offer outstanding performance efficiency, delivering 1.52 DMIPS/MHz within a very small footprint and with extremely low power consumption.
The DesignWare ARC EM Family of processor cores is supported by a robust ecosystem of software and hardware development tools and real-time operating systems. The cores are highly-configurable, enabling designers to optimize the cores for each instance on an SoC to deliver maximum performance and code density with minimum power dissipation and cost.
DesignWare ARC processor cores are supported by a variety of 3rd-party tools, operating systems and middleware from leading industry vendors, including members of the ARC Access Program.
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