DesignWare ARC 700 Processor Core Family 

Overview 

Synopsys' DesignWare® ARC® 700 Family of 32-bit RISC processor cores are ideal for deeply embedded applications and DSP tasks where high performance and low power consumption is required. To address a wide range of processing needs, the DesignWare ARC 700 family includes flexible memory options such as single-cycle Closely Coupled Memories (CCMs) for instructions and data, as well as configurable I-cache and D-cache.

The DesignWare ARC 700 family offers a broad range of processor solutions that enable system-on-chip (SoC) designers to create a wide range of embedded microprocessors that are optimized for their specific target applications. These solutions include the DesignWare ARC 710D, ARC 725D and ARC 770D.

Optional DSP and floating point unit (FPU) capabilities enable designers to address a wide range of processing requirements with a single host application processor. Using a single processor simplifies the design, lowers silicon-area and enables faster debug of the chip.

Synopsys' ARC processors have been used by more than 170 customers worldwide who collectively ship more than 700 million ARC-based chips annually. The DesignWare ARC processors are extendable, allowing designers to add their own custom instructions that dramatically increase performance.

DesignWare ARC processor cores are supported by a variety of 3rd-party tools, operating systems and middleware from leading industry vendors, including members of the ARC Access Program.

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  • ARC 710D
  • Cacheless 32-bit processor for real-time control more

 
Optimized for real-time processing, where high speed and deterministic response are required. Small area, low power and configurable architectural make the core ideal for multi-core applications


 
Full-featured high performance embedded core with best-in-class die area and power characteristics. It is a complete processor solution for complex SoCs targeted at demanding applications in consumer, networking, automotive and other markets. The core’s flexible, configurable memory architecture makes it ideal for RTOS-based applications

  • ARC 770D
  • High-performance processor with MMU and Linux acceleration package more

 
The ARC 770D processor core delivers up to 30% higher performance running Linux, Android or other high-end operation system. The ARC 770D processor core is ideal for embedded multi-core and portable applications

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.



Power and cycle count reduction running sensor application software with APEX accelerators

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.



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