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Integrating sensor data acquisition in mobile applications
Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop
DesignWare Technical Bulletin - DDR4, Processor IP, USB, SATA and more
The MIPI M-PHY Reduces Power In Mobile Chip-To-Chip Interfaces
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Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0....
Fujitsu Semiconductor ASIC Design for 2G/3G/4G Baseband Processor in Volume....
Tektronix Demonstrates MIPI® Alliance M-PHY® Test Solution with Synopsys....
GLOBALFOUNDRIES and Synopsys Partner to Provide Comprehensive Design....
Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for....
Synopsys Accelerates Adoption of FinFET Technology with Production-Proven....
Synopsys Introduces Memory Test and Repair Solution for Designs at 20....
All Synopsys News
Chip Design: Integrating sensor data acquisition in mobile applications
Electronic Design: The MIPI M-PHY Reduces Power In Mobile Chip-To-Chip Interfaces
SemiWiki: How to protect my wallet against hackers? NVM IP solutions...
ChipEstimate.com: The Use of FinFETs in IP Design
EDN: Using audio codecs IP as the digital audio hub in mobile multimedia systems
Chip Design: The Accelerating Demand for 10 Gbps SuperSpeed USB 3.0
Electronic Design: JEDEC UFS Streamlines Storage Interface Development
USB IP Blog: To USB or Not to USB
The Eyes Have it: A Mixed-Signal IP Blog
On the Move: MIPI IP Blog
FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys
From Design to Test: Developing High-Reliability MTP NVM
Synopsys DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications
Obfuscating Attacks on Secure SoCs through Encrypted Code Execution
Twelve Design Techniques for Successful Integration of Data Converter IP into an SoC
Designing with FinFETs: The Opportunities and the Challenges
Mixed-Signal IP Design Challenges in 28-nm Process and Beyond
3 Easy Ways to Accelerate Embedded SoC Development
Achieving Highly Reliable 10G Backplane Designs
Ethernet QoS for use in Automotive Networking Designs
Integrating Audio Functionality into SoCs (Mandarin)
Logic Libraries for High-Performance SoCs
Designing with FinFETs
New PCI Express 3.0 Equalization Requirements
Featured USB Video: Demonstration of USB 3.0 SSIC Compliance Testing with MIPI M-PHY
Featured Ethernet Video: Equalization: Manual or Adaptive
Featured PCIe Video: Minimize High-Speed PHY Risk for First Silicon Success
Featured MIPI Video: Demo of Interop with UFS Host and MIPI UniPro IP
Featured DDR Video: Synopsys Discusses its New DDR4 Memory Interface IP
Featured HDMI Video: Synopsys Demonstrates DesignWare® HDMI Receiver IP Solution with Fast Switching
Featured SATA Video: SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching
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OCZ Achieves First-Pass Silicon Success for SSD Controller Using DesignWare IP and Synopsys Professional Services
Fujitsu Semiconductor Selects DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP for 2G/3G/4G Baseband Design
Case Study: InfoTM Microelectronics and DesignWare USB IP
Case Study: Sunplus IT and DesignWare USB 3.0 IP
Case Study: Guangdong Nufront CSC CO., LTD and DesignWare USB IP
Case Study: Hisense and DesignWare USB IP
Parrot Achieves First-Pass Silicon Success with Synopsys DesignWare Audio Analog Codec and USB 2.0 IP
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