Visit Synopsys in Booth 8 to learn about our high-quality, silicon-proven DesignWare IP portfolio for PCI Express, which includes controllers, PHYs and verification IP. See how our robust IP development methodology, extensive investment in quality, IP prototyping, software development, and comprehensive technical support enables designers to accelerate time-to-market and reduce integration risk.
WHERE: Santa Clara Convention Center, Hall B, Santa Clara, CA
WHEN: June 4-5, 2014
CONFERENCE AND EXHIBIT HOURS: 9:00 a.m. to 5:30 p.m.
For details visit the PCI-SIG web site
Synopsys Booth (Booth 8)
See 4 booth demos and enter to win an Apple iPad mini!
- Synopsys Demos:
- DesignWare Controller IP for PCI Express 4.0
- DesignWare PHY & Controller IP for PCI Express 3.0
- DesignWare PHY IP for PCI Express at 16 Gb/s
- Synopsys Next Generation Verification IP for PCI Express
Synopsys Technical Presentations
PCI Express Controller Design Challenges at 16GT/s
PCI-SIG announced that the next generation of the PCI Express specification will move the maximum data rate from 8GT/s to 16GT/s. While most attention is initially focused on the high-speed SERDES design to achieve 16GT/s, there are substantial implications and challenges for designing the PCIe controller and the application logic to support these data rates. This presentation will offer an in-depth review of the critical design changes and challenges to the controller and application logic design to support the new bandwidth and traffic flow, PHY interface, and clock frequency. Designers and architects considering incorporating 16GT/s PCI Express functionality in their upcoming designs will benefit from attending, particularly those moving from a previous generation of PCI Express.
Presenter: Richard Solomon, Technical Marketing Manager, Synopsys
Date/Time: Wed., June 4, 3:30-4:30 p.m.
Challenges and Benefits of SRIS in PCI Express Systems
Separate Refclk Independent Spread (SRIS) is a new usage model that allows PCIe links to exist outside the box, especially for high data rate PCIe 3.0 (8 Gbps) and upcoming PCIe 4.0 (16 Gbps) systems. SRIS will be used in chassis-to-chassis interconnect in high-end networking systems. This presentation will cover the challenges and benefits of integrating SRIS, including penalties for not sending the Refclk, jitter and EMI implications, and how other standards have dealt with similar issues. Designers and architects of high-end networking systems, as well as anyone using 8 Gbps or 16 Gbps PCI Express in their systems, will benefit from attending this presentation.
Presenter: Michael Lynch, R&D Manager, Synopsys
Date/Time: Thurs., June 5, 1:30-2:30 p.m.
For more information on Synopsys’ DesignWare IP for PCI Express, visit: http://www.synopsys.com/PCIe