SNUG Silicon Valley – IP Summit  

 
IP Summit 2014IP Summit
March 24th- 25th, 2014
Santa Clara Convention Center


Synopsys customers are invited to register for the IP Summit at SNUG Silicon Valley. The IP Summit program consists of highly technical sessions focused on how you can integrate IP into your SoC designs with less risk and improved time-to-market.


TimePresentation Title
Monday, March 24th
11:00-12:30Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM
12:30-2:00IP Lunch and Learn: Physical IP Development on FinFET - There's Nothing Planar About It!
2:00-3:30Hardening DSPs for Performance and Power with DesignWare Logic Libraries and Embedded Memories - Presented by CEVA
3:45 – 5:15Yes! You Can Use PCI Express for Mobile and Enterprise SoCs
Tuesday, March 25th
10:30-12:00Integrating USB 3.1 in Your Next SoC Design
1:30-3:00Addressing the Challenges of Multi-Protocol High Speed PHY Design
3:45-5:15Designing Compound Floating Point Units with an Efficient Pre-Validated IP Based Approach

Related Session

TimePresentation Title
Wednesday, March 26
3:00-4:30SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System

REGISTER NOW for the IP Summit


Monday, March 24th

MA-08: Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM (11:00-12:30)
DDR SDRAM devices continue to evolve, and mobile devices like LPDDR4 are getting faster and more mainstream than their "PC" DDR counterparts, such as DDR3/4. Even though 3200Mb/s is achievable with both LPDDR4 and DDR4, these interfaces are significantly different compared to the mobile and PC DRAMs that preceded them. What follows LPDDR4 and DDR4 is a technologically challenging roadmap featuring several application specific DRAMs. This presentation compares the requirements of LPDDR4 IP against those for DDR4 IP. It also examines how a low-power PHY can be made to run at 3200Mb/s with the new LPDDR4 features and signaling in a mobile application compared to the reliability, availability, and serviceability features of the DDR4 IP, enabling DDR4 to meet the requirements for enterprise/server/storage SoCs. We will also look at next generation DRAM technologies that may replace or complement LPDDR4 and DDR4 (90 min)

MA-11: IP Lunch and Learn: Physical IP Development on FinFET - There's Nothing Planar About It! (12:30-2:00)
To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That includes scaling, lower power consumption and higher speeds. To achieve this, analog/mixed-signal development techniques and design styles have to be re-created and implemented with very close foundry cooperation. This session discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries. In addition, this presentation will highlight the methodologies that incorporate advanced process qualification vehicles.

MB-08: Hardening DSPs for Performance and Power with DesignWare Logic Libraries and Embedded Memories - Presented by CEVA (2:00-3:30)
Devices continue to require better performance and longer battery life, demanding SoCs to deliver excellent speed and consume less power. DSP cores play a key role in SoCs targeting a wide range of end products, from smartphones and wearable devices, to wireless infrastructure. Depending on the application, these core implementations may target high or low speeds but they always seek to keep area and power dissipation very low. In this session, CEVA will present results and best practices in hardening DSP cores to achieve performance targets, while consuming low-power and minimal area utilizing Synopsys' 28-nm DesignWare Logic Libraries and Memory Compilers as well as Synopsys' implementation and signoff tools. CEVA will also show how choosing the correct IP and methodology helps achieve optimal results as well as discuss best practices to fine tune the results to reduce leakage power. (90 min)

MC-08: Yes! You Can Use PCI Express for Mobile and Enterprise SoCs (3:45 – 5:15)
This presentation explores the evolution of PCI Express from its prior server and desktop focus to spanning the entire spectrum from ultra-mobile devices to high-performance computing. First, it will describe how the new M-PCIe ECN, along with existing features such as L1 sub-states and Readiness Notifications, enable PCI Express to save power and extend battery operation in mobile products appearing in the 2014-2015 timeframe. The presentation will then discuss the 16GT/s signaling rate announced as part of the upcoming PCI Express 4.0 Base Specification and how it serves the high-performance computing environment. The presentation will also cover key issues facing designers incorporating these new PCI Express features in both mobile and enterprise spaces, including bandwidth and clocking considerations, PHY interfaces, power management impacts, and link-related tradeoffs. (90 min)

Tuesday, March 25

TA-09: Integrating USB 3.1 in Your Next SoC Design (10:30-12:00)
The presentation explores the evolutionary and revolutionary changes between USB 3.0 and USB 3.1 and how they affect host controllers, hubs, and PHY IP. The presentation will also describe the challenges of designing a USB 3.1 consumer SoC, based on lessons learned from real USB 3.0 implementations. Furthermore, the session discusses how applications such as mass storage and communication can benefit from the high throughput of USB 3.1. The presentation will conclude with examples of multi-purpose SoC implementations that incorporate USB 3.1 as well as a range of connectivity protocol interfaces like USB 3.0, SSIC, LLI, UFS, M-PCIe, and PCI Express. (90 min)

TB-09: Addressing the Challenges of Multi-Protocol High Speed PHY Design (1:30-3:00)
As the cost of IC design rapidly increases due to the reduction in feature sizes, companies are no longer designing products that target just a single application. Instead, ICs are architected to utilize multi-protocol physical layer (PHY) IP which can be connected to multiple different protocol-specific physical coded sub-layers and controllers. This augments the functionality of the device, enabling programmability and reducing the overall design cost. The presentation describes the design challenges addressed by a 12.5 Gbps PHY that supports a range of protocols and electrical specifications, all requiring different reference clock inputs, specific jitter requirements, and wide range of line rates. (90 min)

TC-09: Designing Compound Floating Point Units with an Efficient Pre-Validated IP Based Approach (3:45-5:15)
With PCI Express continuing to be the de-facto interconnect for Cloud computing systems, there is a growing need for functionality to address the increased storage requirements as well as greater path loss and equalization complexity at 8 GT/s. This tutorial discusses how the PCI Express interconnect is addressing storage requirements in server-based SoCs with standards such as SATA Express and NVM Express. In addition, we will examine the need for active repeaters to help compensate for the significant path loss at 8 GT/s and other developments in the specification to support the continued development of Cloud-based computing. Since the PCI Express protocol doesn’t stop at servers, this session also examines how the latest PCI Express features help designers address low power requirements in mobile applications including Optimized Buffer Flush/Fill (OBFF), latency tolerance reporting (LTR), L1 sub-states and the new M-PHY over PCI Express standard. (90 min)

Related Session

Wednesday, March 26

WC-02: SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System (3:00-4:30)
SoC test becomes significantly more complex as designs become larger and the amount and variety of IP used increases. Today's SoC present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity, and new defects at small geometries (FinFET). We will discuss new features and capabilities of the DesignWare STAR Memory System, Synopsys' memory test, repair and diagnostics solution, that address these challenges. In addition, we will describe the unique capabilities of the DesignWare STAR Hierarchical System, a hierarchical test solution for all IP/cores on your SoC including interface IP, analog/mixed signal IP, and digital logic blocks. (90 min)

REGISTER NOW for the IP Summit



NewsArticlesBlogsWhite PapersWebinarsVideosNewslettersCustomer Successes