Intel Developer Forum 2014 

See Synopsys Demonstrations on 10G USB 3.1, PCI Express 4.0 at 16 Gbps and more 

For over a decade, the Intel Developer Forum (IDF) has been Intel's premier conference, helping to shape the direction of tomorrow's technology. IDF brings together people from every part of the technology world to experience visionary keynotes, technology and industry insights, and technical sessions (including lectures, interactive panels, hands-on labs and Q&As). In addition, the Technology Showcase hosts exhibits and demonstrations from Intel and leading technology companies.

Synopsys will showcase its latest developments in DesignWare® IP for USB and PCI Express® in the SuperSpeed USB and General Communities.

Dates: September 9-11, 2014

Where: Moscone Center West, 800 Howard Street, San Francisco, CA 94103

Technology Showcase Hours:
Tuesday, September 9, 11:00 am-7:00 pm
Wednesday, September 10, 11:00 am-1:00 pm & 4:00 pm-7:00 pm
Thursday, September 11, 11:00 am-2:00 pm
Synopsys Highlights at IDF

General Community - booth 655

  • DesignWare PCI Express 4.0 Controller IP
    Synopsys will demonstrate the industry’s first PCI Express 4.0 Controller IP in the General Community. Using coreConsultant, designers can configure the DesignWare PCIe® 4.0 IP for their specific SoC requirements, including 16 Gbps data rates.
  • DesignWare PHY IP for PCI Express at 16 Gbps
    View Synopsys’ 16 Gbps SerDes technology demonstration in the General Community. The 28-nm test chip includes four channels of high-speed 16 Gbps SerDes that are accessible through a graphic user interface for PHY configuration setup and performance monitoring.

SuperSpeed USB Community - booth 773

  • USB 3.1 IP Technology Demonstration
    Synopsys will show 10 Gbps transfers over USB 3.1 using the Synopsys USB 3.1 Device and Host controller IP on Synopsys' HAPS® FPGA-based prototyping platforms.
  • DesignWare USB 3.0 femtoPHY IP for 14-/16-nm FinFET Processes
    With up to 50% smaller die area and low power optimization for FinFET processes, the DesignWare USB femtoPHY IP minimizes USB PHY silicon cost while extending battery life. The demonstration shows the femtoPHYs’ margin in a 14-/16-nm FinFET process.
  • DesignWare USB 3.0 SSIC Host and Device IP with MIPI M-PHY
    USB 3.0 SuperSpeed InterChip (SSIC) uses USB 3.0 protocols and the low power MIPI M-PHY for connecting WiFi and modem chips to mobile application processors to reduce power consumption by up to 67% in mobile phones, tablets, and phablets. Synopsys will demonstrate the DesignWare USB 3.0 Host with MIPI M-PHY connected to a USB 3.0 Device with MIPI M-PHY on a HAPS FPGA-based prototyping platform from Synopsys.

Additional Resources:
Read more about PCI Express IP
Read more about USB IP
View DesignWare IP videos

For more information or to register, go to Intel Developer Forum 2014.

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