 From Design to Test: Developing High-Reliability MTP NVM | In developing high-quality and reliable MTP NVM, NVM IP providers must account for design and architectural considerations as well as comprehensive silicon testing. To help system-on-chip (SoC) designers select the highest reliability NVM IP, this white paper will review the key considerations involved in the entire process from design to test, including: key reliability specifications; designing-in reliability; and demonstrating reliability through characterization, qualification, and reliability testing.
Martin Niset, Senior Engineering Manager, Synopsys, Inc.; Craig Zajac, Senior Product Marketing Manager, Synopsys, Inc. |
| | Synopsys DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications | This paper describes Synopsys’s DesignWare® ARC™ EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores. This paper is sponsored by Synopsys, but all opinions and analysis are those of the author.
J. Scott Gardner, Senior Analyst, The Linley Group |
| | Twelve Design Techniques for Successful Integration of Data Converter IP into an SoC | Data converter IP integration is sometimes perceived as complex because it requires careful custom place-and-route. However, by understanding the potential issues that can impact performance, an SoC designer has all the tools for successful integration that delivers the expected performance. This white paper provides twelve simple design techniques that address all the common issues of integration in a methodical way and help ensure the successful integration of high-performance data converters in SoCs.
Roberto Guerreiro, Application Engineering Manager, Synopsys, Inc ; Manuel Mota, Technical Marketing Manager, Synopsys, Inc. |
| | Designing with FinFETs: The Opportunities and the Challenges | Although planar CMOS technology continues to scale to 20-nanometer (nm) and beyond, FinFET technology offers superior attributes and demonstrates better results in the areas of performance, leakage and dynamic power, intra-die variability, and retention voltage for SRAMs. Although FinFETs are emerging as the device technology of choice at these advanced nodes, they introduce new design challenges that require knowledge of and experience in designing with FinFETs to ensure design success.
Jamil Kawa, R&D Group Director, Synopsys, Inc. |
| | Technical Considerations for Implementing USB 3.0 on SoCs | This paper highlights the specific features and enhancements in the USB 3.0 protocol. These
enhancements come with technical complexities, and this paper outlines complexities and the resulting
design challenges. It shows how a USB 3.0 core's reconfigurability can broaden a design's potential
applications and reuse. Finally, it talks about USB 3.0 selection and implementation considerations, from
architecture, prototyping, and software, to testing and certification.
Gervais Fong, Senior Product Marketing Manager, Synopsys, Inc.; Eric Huang, Senior Product Marketing Manager, Synopsys, Inc. |
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