|Featured PCIe Video: Prioritizing PCI Express 3.0 Bandwidth using DesignWare IP for PCIe|
High-performance I/O applications require moving multiple threads of data simultaneously. The DMA engine of the DesignWare IP for PCI Express 3.0 offloads SoC resources and maximizes the bandwidth of PCI Express 3.0 at 8.0 GT/s. This video showcases the ability of the DMA engine of the DesignWare® IP for PCI Express 3.0 to efficiently allocate bandwidth across multiple channels based on the application's requirements.
Richard Solomon, Technical Marketing Manager for PCI Express, Synopsys
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|Featured USB Video: Industry First: |
USB 3.0 SSIC Host and Device with MIPI M-PHY Demonstration
View the industry's first demonstration of USB 3.0 Device and Host IP running on a MIPI M-PHY. The DesignWare USB 3.0 SSIC Controller IP supports standard PHY interfaces, including MIPI M-PHY, UTMI/UTMI+, ULPI and PIPE. The multi-gear DesignWare MIPI M-PHY, compliant with the version 3.00 specification, supports High-Speed Gear3 operation as well as Gears 1 and 2.
Eric Huang, Product Marketing for USB Digital IP, Synopsys and Hezi Saar, Product Marketing for MIPI IP, Synopsys
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|Designing IP for FinFET Technology: The Opportunities and Challenges|
FinFETs are emerging as the device technology of choice at advanced nodes. This introduces new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This video describes the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.
Jamil Kawa, R&D Director, Synopsys
|Featured Ethernet Video: Equalization: Manual or Adaptive|
Understand what adaptive equalization is and how it relates to CTLE or DFE equalization in a PHY.
Rita Horner Sr. Technical Marketing Manager, Mixed Signal IP, Synopsys, and David Rennie, Sr. Analog Design Engineer, Mixed Signal IP, Synopsys
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|Featured MIPI Video: Demo of Industry’s First MIPI M-PHY Operating in HS-Gear3|
This demonstration shows the industry’s first HS-Gear3 MIPI® M-PHY as tested on Tektronix equipment. The DesignWare® MIPI M-PHY performance results are shown from the transmitter side of the equipment as well as the results of PBRS test pattern generation on the receiver side.
Hezi Saar, Product Marketing for MIPI IP, Synopsys and Chuan Shin Tan, Application Engineer, Tektronix
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|Featured DDR Video: Synopsys Discusses its New DDR4 Memory Interface IP|
Sean O'Kane from ChipEstimate.com interviews Navraj Nandra about the Synopsys' DesignWare DDR4 IP product release. They discuss DDR4 SDRAM, its market, and their predictions for DRAM.
Navraj Nandra, Synopsys and Sean OKane, ChipEstimate.com
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|Featured HDMI Video: Synopsys Demonstrates DesignWare® HDMI Receiver IP Solution with Fast Switching|
See how Fast Switching technology reduces HDMI switching time from 5 seconds to 1 second. Using a BluRay player and a multimedia player, this video demonstrates the DesignWare HDMI Receiver IP solution's high-performance interoperability.
Antonio Costa, R&D Manager for the DesignWare HDMI Controller IP solutions, Synopsys
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|Featured SATA Video: SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching|
See how DesignWare SATA host controller IP issues read/write commands to Port Multiplier-attached drives, while FIS-based switching interleaves the data packets to enhance the utilization of the 6 Gbps SATA link bandwidth
Mat Loikkanen, SATA R&D, Synopsys
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|Featured Analog Video: Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution|
Synopsys shows the next generation DesignWare ADC IP 12-bit 250 MSPS, delivering outstanding performance, robustness and ultra low power dissipation of up to 50% less than previous generations.
Manuel Mota, Technical Marketing Manager, Synopsys and José Carmo, Application Engineer, Synopsys
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|Synopsys Demonstrates DesignWare STAR Silicon Browser IP for Embedded Memory Test and Repair|
This demonstration will feature the post-silicon interactive automation capabilities of the DesignWare STAR Silicon Browser, which utilizes the DesignWare STAR Memory System's embedded test & repair IP solution.
Yervant Zorian, Chief Architect, Synopsys, Gevorg Torjyan, R&D Engineer, Synopsys
|Industry’s First Complete Audio IP Subsystem|
Learn how the pre-integrated, configurable DesignWare® SoundWave Audio Subsystem helps you achieve great audio with a complete, SoC-ready subsystem solution. Also, join us in the Synopsys Sound Room, where we test our high-definition audio solutions, to see the SoundWave Audio Subsystem in action using a HAPS® FPGA-Based Prototyping System.
Henk Hamoen, Sr. Product Marketing Manager, Synopsys