Visit Synopsys at the PCI-SIG Developers Conference 2013 to see DesignWare® IP demonstrations for PCI Express® 3.0 and M-PCIe™. The PCI-SIG DevCon is designed to help member companies develop and bring new products utilizing the PCI Express interface to the market. In booth Synopsys will be demonstrating the industry's most complete PCI Express 3.0 and M-PCIe solutions, including the industry's only complete solution to earn PCI-SIG Certification for PCI-Express 3.0.
WHEN: June 25 – 26, 2013
WHERE: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA 95054
CONFERENCE AND EXHIBIT HOURS: 9:00 am to 5:00 pm. For details visit the PCI-SIG web site
Technical Presentations by Synopsys
June 25 at 4:30pm
Migrating PCIe Designs to M-PCIe
Speaker: Richard Solomon
This presentation will cover key issues facing PCIe designers looking to support the upcoming M-PCIe ECN. Topics will include bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to various choices around LTSSM and other link-layer changes. The presentation will also discuss what effects these changes can have on the transaction and application layers of devices moving from PCIe to M-PCIe.
June 26 at 1:30pm
PCI Express' New Low Power Modes Driving Tablets, Cloud
Speaker: Navraj Nandra
Low power requirements are creating innovations in the implementation of PCI Express. Techniques such as employing L1 sub-states, low leakage modes, reference clock repeaters and on-chip clock distribution are being implemented in tablet applications in either root complex or end point configurations. In the enterprise cloud, power budget for PCI Express 3.0 deems a trade-off between designing an efficient transmitter with enough launch amplitude to the receiver that has just the right amount of equalization to support channel loss. This presentation will offer design insights for these two different use cases with real-world examples.
See 2 demos to enter to win an iPad at the booth!
DesignWare Controller IP for M-PCIe
The new M-PCIe ECN was designed to support the needs of very low-power PCI Express devices while maintaining the benefits of the PCI Express protocol. The DesignWare Controller IP for M-PCIe leverages the market-leading DesignWare Controller IP for PCIe 3.0 to provide designers with a full implementation of the M-PCIe ECN. The demonstration will showcase the DesignWare IP solutions supporting the new M-PCIe specification from PCI-SIG.
DesignWare IP for PCI Express 3.0 DMA Performance at 8.0 GT/s
Today’s high-performance I/O applications require moving multiple threads of data simultaneously. The DMA engine of the DesignWare IP for PCI Express 3.0 offloads SoC resources and maximizes the bandwidth of PCI Express 3.0 systems to 8.0 GT/s. This demonstration showcases the ability of the DMA engine of the DesignWare® IP for PCI Express 3.0 to efficiently allocate bandwidth across multiple channels.
Getting the most out of your PCI Express verification using advanced VIP and debug
Integration testing of a core into an SoC has its own unique challenges and is far from trivial. Teams need to configure the IP/IIP, run extensive real-life traffic, and inject common error conditions, while ensuring functional coverage goals are met. This demonstration highlights the use of VIP to optimize and accelerate the process of integration testing. It proposes an optimal strategy for developing integration tests using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection, verification plan signoff, and protocol debug.
For more information on Synopsys’ DesignWare IP for PCI Express, visit: http://www.synopsys.com/IP/InterfaceIP/PCIExpress/Pages/default.aspx