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DesignWare Technical Bulletin
DesignWare Technical Bulletin – Q1–13
FinFET Design, Manufacturability, and Reliability
Embedded Memory Test & Repair at 20-nm Nodes and Below
Efficient Audio Processing with DesignWare ARC™ Audio Processors
Ethernet QoS v4.0 Controller for 802.1 Compliant Networks
Virtualizer Development Kits: Fast Track to DesignWare Software Prototyping
Transitioning from USB 2.0 HSIC to USB 3.0 SSIC
DesignWare Technical Bulletin - Q4-12
Using L1 Sub-States to Reduce Power Consumption in PCI Express®-Based Devices
HDMI Fast Switching
Performance and Coding Advantages with the ARC™ XY Memory DSP Option
Interfacing an SoC to the Real World with Data Converter IP
MHL: The New Mobile-to-TV Protocol
DesignWare Technical Bulletin – Q3-12
Selecting Standard Cell and Memory IP to Meet Chip Goals
Managing Design Complexity with a Complete Audio IP Subsystem
Building an IP-XACT Design and Verification Environment with DesignWare IP and core Tools
A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes
Synopsys Verification IP, What’s New?
DesignWare Technical Bulletin - Q1-12
SuperSpeed USB 3.0 Rises in Smartphones
Embedded Design Prototyping Relies on IP Model Availability
DesignWare Technical Bulletin - Q4-11
DesignWare minPower Components
DesignWare Interface IP Goes Virtual
DesignWare Technical Bulletin - Q2-10
Propelled by HDMI, the First 3D Devices Hit the Shelves
DesignWare Mobile Storage Host Controller Core: Handling Timing Requirement for SD3.0 Cards
DesignWare Technical Bulletin - Q1-10
DesignWare Library 2010.03 Release
The DesignWare HDMI 1.4 IP Solutions Revolutionize Home Theatre Multimedia Devices
DesignWare minPower Components 2010.03 Release
Accelerate the Development of Mobile Device with New DesignWare MIPI IP
Synopsys Introduces Industry's First SystemC SuperSpeed USB 3.0 TLM-2.0 Models
New DesignWare OCP Verification IP 3.0 Features
DesignWare Technical Bulletin - Q3-09
Choosing the Right Architecture for Analog-to-Digital Conversion in Wireless Broadband Communications AFEs
Advanced Audio Drivers - The Rising of a New Class of Drivers
New Features for DesignWare DDR3/DDR2 SDRAM Memory Controller IP
DesignWare minPower Components Slash Power in Datapath Circuit
MIPI: Driving Innovation in the Mobile Industry
DesignWare Technical Bulletin - Q2-09
Introducing the Hybrid Architecture for the DesignWare Interconnect Fabric for the AMBA 3 AXI protocol
Synopsys Enables System Design Interoperability with System-Level Catalyst Program
DesignWare DDR3/2 PHY
Beating the Odds on OCP Slave Memory Behavior
Synopsys Releases DesignWare SATA IP for New SATA 6Gb/s Data Transfer Rate
Getting to Market Early With SuperSpeed USB Virtual Platforms
Synopsys Verification IP Alliance
DesignWare Technical Bulletin - Q1-09
What's New in 2008.09 DesignWare Library Datapath and Building Block IP
New VMM-Enabled PCI Express System Example
New Release of DesignWare OCP Verification IP
DesignWare Technical Bulletin - Q3-08
Connecting a Standard SRAM Device to an AMBA 3 AXI Subsystem Using the DesignWare Generic Slave
How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
DesignWare Verification IP Quickstart for AMBA 3 AXI: A New View into Documentation
New Release of DesignWare Verification IP for OCP
DesignWare Technical Bulletin - Q2-08
PCI Express Switch Enumeration Using VMM-Based DesignWare Verification IP
USB 2.0 IP with Link Power Management Extension
Functional Coverage Techniques: Leveraging DesignWare Verification IP and VMM for Efficient Testbenches
Virtualize Your Connectivity IP with DesignWare System-Level Library
DesignWare Technical Bulletin - Q1-08
Synopsys Enhances DesignWare IP for DDR2 and DDR3
Update to Six DesignWare Building Block IP Application Notes
USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Know Your Protocol: A Verification IP Perspective
DDR2/3 SDRAM Controller Options: Protocol or Memory Controller
Building a Bridge from PCI Express to AMBA 3 AXI On-Chip Bus
Latest DesignWare IP SolvNet Articles
DesignWare Technical Bulletin - Q4-07
New Datapath and Building Block IP in 2007.12 Release of the DesignWare Library
Tradeoffs Between Combinational and Sequential Dividers
Low Power Methodology Demystified: Insights into the LPMM
Understanding the DesignWare USB 2.0 Host Controller's New Feature for OHCI Clocks
PCI Express 2.0: Comparing 2.5-Gbps Solutions Versus 5.0-Gbps
New SolvNet Articles for DesignWare IP for AMBA
DesignWare Technical Bulletin - Q3-07
A Cheat Sheet for the DesignWare Solutions for AMBA IP
A Guide to Understanding the Latest Enhancements for DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric
Synopsys Enhances DesignWare Synthesizable IP for AMBA 3 AXI Interconnect Fabric
Get the Latest Product Information on DesignWare IP Through myDesignWare.com
Extending Open Core Protocol (OCP) Functionality with VMM: Implementing a Slave Memory for Verification IP
Synopsys DesignWare Verification IP Supports PCI Express Gen II and PIPE 1.87 Specifications
DesignWare Technical Bulletin - Q2-07
Overview of 2007.04a Release of DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI
New Download and Installation Process for DesignWare Synthesizable IP for AMBA 2.0 and AMBA 3 AXI
DDR2 SNUG Tutorial: DDR2-533 and Beyond with DesignWare Memory Interface IP
Pipelining with DesignWare Building Block IP
Latest Update to DesignWare Documentation and STARS-on-the-web
An Introduction to Synopsys' New SATA AHCI Digital Core Solution
New Release of DesignWare Verification IP for I2C is now available for download
DesignWare Technical Bulletin - Q1-07
2007.03 DesignWare Library Datapath and Building Block IP - DesignWare® Library introduces 19 new Building Block IPs in the 2007.03 release
IP and TCP/UDP Checksum Offload Functionality and its Support in Synopsys' DesignWare Ethernet MAC 10/100/1000 - Universal Core
New SolvNet articles on DW IIP, VIP and DW Cores featuring AMBA, PCI Express and more
Updates to TSMC Nexsys Libraries for the 65-nm and 90-nm Process Technology
DesignWare Verification IP adds support for SystemVerilog and VMM in VCS-MX
DesignWare Verification IP for OCP 2.1 (Open Core Protocol) - Now at Production Release and Ready for Download
DesignWare Introduces Port Monitor Verification IP for the AMBA 3 AXI Protocol
DesignWare Verification IP adds native performance in VCS for Verilog-based Testbenches
DesignWare Technical Bulletin - Q4-06
Using DW_ahb_dmac in an AXI Subsystem
Connecting an AMBA 2.0 AHB Subsystem to an AMBA 3 AXI Subystem
DesignWare Introduces the AMBA 3 AXI to APB3 Bridge and Fabric Synthesizable IP
DesignWare Introduces Bi-Directional Command Support in Interconnect Fabric for AMBA 3 AXI
Performance of Different Multipliers in the DesignWare Building Block IP
DesignWare Technical Bulletin - Q3-06
coreTools 2006.03 is now available
What's New in 2006.06 DesignWare Library Datapath and Building Block IP
New Floating Point Components in DesignWare Library
XGXS-PCS IP - PCS for 10G Ethernet eXtender Sublayer
DesignWare Technical Bulletin - Q2-06
Deciding on FIFO Sizes When Implementing DW Digital Cores
New Issue
DesignWare Technical Bulletin - DDR4, Processor IP, USB, SATA and more
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The MIPI M-PHY Reduces Power In Mobile Chip-To-Chip Interfaces
ARTICLE
Using audio codecs IP as the digital audio hub in mobile multimedia system
Webinar
Achieving Highly Reliable 10G Backplane Designs
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News
Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0....
Fujitsu Semiconductor ASIC Design for 2G/3G/4G Baseband Processor in Volume....
Tektronix Demonstrates MIPI® Alliance M-PHY® Test Solution with Synopsys....
GLOBALFOUNDRIES and Synopsys Partner to Provide Comprehensive Design....
Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for....
Synopsys Accelerates Adoption of FinFET Technology with Production-Proven....
Synopsys Introduces Memory Test and Repair Solution for Designs at 20....
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All Synopsys News
Articles
Electronic Design: The MIPI M-PHY Reduces Power In Mobile Chip-To-Chip Interfaces
SemiWiki: How to protect my wallet against hackers? NVM IP solutions...
ChipEstimate.com: The Use of FinFETs in IP Design
EDN: Using audio codecs IP as the digital audio hub in mobile multimedia systems
Chip Design: The Accelerating Demand for 10 Gbps SuperSpeed USB 3.0
Electronic Design: JEDEC UFS Streamlines Storage Interface Development
Insight: ARC EM Starter Kit Accelerates Embedded Software Development
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Blogs
Express Yourself
Configurable Thoughts
USB IP Blog: To USB or Not to USB
The Eyes Have it: A Mixed-Signal IP Blog
On the Move: MIPI IP Blog
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White Papers
FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys
From Design to Test: Developing High-Reliability MTP NVM
Synopsys DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications
Obfuscating Attacks on Secure SoCs through Encrypted Code Execution
Twelve Design Techniques for Successful Integration of Data Converter IP into an SoC
Designing with FinFETs: The Opportunities and the Challenges
Mixed-Signal IP Design Challenges in 28-nm Process and Beyond
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Webinars
3 Easy Ways to Accelerate Embedded SoC Development
Achieving Highly Reliable 10G Backplane Designs
Ethernet QoS for use in Automotive Networking Designs
Integrating Audio Functionality into SoCs (Mandarin)
Logic Libraries for High-Performance SoCs
Designing with FinFETs
New PCI Express 3.0 Equalization Requirements
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Videos
Featured PCIe Video: Minimize High-Speed PHY Risk for First Silicon Success
Featured USB Video: MCCI and Synopsys Demonstrate USB 3.0 MTP
Featured MIPI Video: Demo of Interop with UFS Host and MIPI UniPro IP
Featured DDR Video: Synopsys Discusses its New DDR4 Memory Interface IP
Featured HDMI Video: Synopsys Demonstrates DesignWare® HDMI Receiver IP Solution with Fast Switching
Featured SATA Video: SATA Host IP Demo Using a Port Multiplier and FIS-Based Switching
Featured Analog Video: Synopsys Demonstrates Next Generation DesignWare Data Converter IP solution
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Newsletters
DesignWare Technical Bulletin Current Issue
DesignWare Technical Bulletin Archive
Synopsys Insight
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Customer Successes
OCZ Achieves First-Pass Silicon Success for SSD Controller Using DesignWare IP and Synopsys Professional Services
Fujitsu Semiconductor Selects DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP for 2G/3G/4G Baseband Design
Case Study: InfoTM Microelectronics and DesignWare USB IP
Case Study: Sunplus IT and DesignWare USB 3.0 IP
Case Study: Guangdong Nufront CSC CO., LTD and DesignWare USB IP
Case Study: Hisense and DesignWare USB IP
Parrot Achieves First-Pass Silicon Success with Synopsys DesignWare Audio Analog Codec and USB 2.0 IP
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