 | IP Summit
Wednesday March 28
Santa Clara Convention Center
The IP Summit program consists of nine sessions focused on how you can easily integrate IP into your SoC designs with less risk and improved time-to-market. Don’t miss our special luncheon with guest speaker Suk Lee, Director of Design Infrastructure Marketing Division, TSMC |
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Wednesday, March 28, 10:30-12:00 noon
WA5: Best Practices for Implementing Memories and Libraries to Deliver Superior PPA and Embedded Test & Repair
Selection of memory compilers and logic libraries has significant impact on the power, performance and area of SoC designs. This tutorial presents best practices for implementing the optimal combination of memories, libraries and embedded test and repair to meet your design requirements. Also learn how the DesignWare Memory Compilers and Logic Libraries are used in conjunction with Synopsys tools including ICC and DC to deliver a high-performance, low-power and differentiated SoC design. Benchmarks on CPU and GPU implementations will also be shared. (90 min)
WA6: Designing to the New PCI Express 3.0 Equalization Requirements
PCI Express® 3.0 has changed the type of equalization it uses over previous generations. This tutorial will discuss why equalization is required, the decision feedback and continuous-time linear equalization types used by PCI Express, equalization circuits within the PHY, feedback methods across the PIPE interface and across the Link, convergence algorithms and issues with the current PIPE specification and debug features implemented. (60 min)
WA7: Tag – You’re it! Passive, Unclonable RFID Tags Made Possible
Verayo combined Physical Unclonable Function technology, Synopsys’ DesignWare Non-Volatile Memory (NVM) IP and the ISO 14443-A protocol to realize a passive, unclonable, RFID tag. NVM IP selection required careful consideration including process technology, low-power operation, configuration and area. The NVM IP was subjected to parametric and 1000 hour accelerated-life testing. Approximately 31,000 devices were baked at 150oC, with read/write stress testing at 168, 500, 1008 hour intervals; results yielded no observed failures in the NVM. In this session, Verayo discusses how their PUF technology and Synopsys’ NVM IP enabled a cost-effective, unclonable RFID tag. (60 min)
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Wednesday, March 28, 12:00 – 1:15 Lunch and Learn with Guest Speaker, Suk Lee,
Director of Design Infrastructure Marketing Division, TSMC.
The Scaling Factor: Impacts of Process Migration on IP Design.
Wednesday, March 28, 1:15 – 2:45 pm
WB5: Meeting Quality of Service Requirements with DDR Memory Controllers
DDR memory latencies in number of clock cycles continuously increase with each new DDR family and DDR4 is no different. At the same time, more masters with different types of applications are sharing the same DDR interface to reduce bill-of-materials. This makes it very challenging to define and meet QoS requirements of a SoC without sacrificing much memory bandwidth. This tutorial discusses QoS requirements such as minimum average latency, minimum bandwidth, or maximum latency for different applications. It also outlines optimization techniques that can be used for DDR memory controllers to address QoS. (60 min)
WB6: Create a Complete Audio IP Subsystem for Your SoC in Minutes
Audio requirements for products continue to grow: devices become internet-connected, multi-channel content is everywhere, plus consumers want features like virtual surround sound. The industry continues to demand shorter time-to-market, lower risk and lower cost. This can be accomplished by using pre-integrated, pre-verified IP subsystems that take away all the traditional hardware and software efforts, and providing seamless plug-in to the application (software) on the host processor. This session discusses how the DesignWare Home Audio IP Subsystem enables designers to create a complete audio solution for their SoCs in a matter of minutes. (90 min)
WB7: Getting the Most from Synthesis to Improve Your Datapath QoR
With Datapath content increasing in today’s designs, it is more important than ever to understand how to take advantage of the advanced datapath features in your implementation flow. This session will review recent and upcoming updates to the DesignWare Datapath IP that can help you achieve the QoR goals in your design. New features including internal rounding in the top down compile flow and datapath extraction analysis capabilities will be the focus of this presentation. Additionally, a brief refresher of the Datapath RTL coding guidelines will also be presented. (60 min)
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Wednesday, March 28, 3:30 – 5:00 pm
WC5: USB 3.0: Ready, Set, Integrate!
With over 70 million USB 3.0 host chips shipped in 2011, early mainstream adoption of USB 3.0 starts now. Are you ready? Synopsys’ USB 3.0 engineers explains how to configure and integrate the DesignWare USB 3.0 digital core into a design, connect it to the DesignWare USB 3.0 PHY, and test a design in a HAPS FPGA prototyping platform. We will discuss technical challenges and how to overcome them from RTL integration to FPGA synthesis, place and route, timing closure, software driver implementation, and interoperability testing. (60 min)
WC6: Future Mobile Interfaces and Integration of MIPI DigRF in Mobile Baseband Processors
Today’s mobile SoC systems require advanced features, better performance and longer battery life in mobile devices. This session introduces new mobile interfaces for highly configurable systems that enable standard connectivity. We will also present a design incorporating MIPI DigRFv4 interface and discuss the integration effort associated with the development of a complete baseband to RFIC application. (90 min)
WC7: The Role of IP in More Moore and More than Moore
Known as “more Moore”, high-k metal gate dielectrics, double patterning and FinFet have extended Moore’s law to 14-nm. Targeting the next generation application processors for tablets and super smartphones, the benefits are performance, lower power and area. Typically at 65-nm and above, “More than Moore” - innovation occurs with integrated sensors and near field communication technologies in applications such as smart-posters and radio frequency identification. In both cases IP is required but has a different design requirement. This tutorial provides a detailed technical review of these technology innovations, the design and implementation challenges for analog and physical IP. (90 min)
REGISTER NOW for the IP Summit