|Securing the Internet of Things Using Hardware Rooted Processor Security - An Architect’s Guide|
Security is a key requirement for Internet of Things (IoT) devices and must be considered for all aspects of the design. This paper provides an overview of security basics, feature requirements, technical solutions, and associated system-level trade-offs for implementing security in IoT devices. Making the required trade-offs is significantly easier by leveraging secure, proven building blocks that were designed with secure systems in mind and optimized for low footprint and energy. This paper can help you decide on the optimal mix of features and best tradeoffs to make for your specific IoT device that will result in a secure architecture that can be efficiently implemented.
Ruud Derwig, Senior Staff Engineer, Synopsys
|Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain|
Read about key challenges in DSP implementation from both hardware and software application perspectives, and learn how a properly selected and configured DSP processor coupled with an advanced software development toolchain can overcome these challenges. This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
Abhishek Bit, CAE, Synopsys; Jamie Campbell, CAE, Synopsys; Sergey Yakushkin, R&D Engineer, Synopsys
|Safety in SoCs: Accelerating the Road to ISO 26262 Certification for the ARC EM Processor|
Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deployed in safety-critical applications, adhering to functional safety standards such as ISO 26262 has become an important consideration when defining the verification methodology. This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.
Steven Parkinson, R&D Engineer, Synopsys
|Real-Time Trace: A Better Way to Debug Embedded Applications |
Firmware and application software development is often the critical path for many embedded designs. Problems that appear in the late phases of the development can be extremely difficult to track down and debug, thus putting project schedules at risk. Traditional debug techniques cannot always help to localize the issue. This whitepaper shows the benefits of debugging with ‘real-time trace’ hardware assistance, including how it can vastly reduce the amount of time needed to track down problems in the code, and introduces other benefits, such as hot-spot profiling and code coverage, offered by real-time trace systems.
James Campbell, CAE, Synopsys, Inc.; Valeriy Kazantsev, CAE, Synopsys, Inc.; Hugh O’Keefe, Engineering Director, Ashling Microsystems
|ARC HS38 Processor: Single- and Multicore CPU Cores for High-Speed Linux Processing on an Embedded Budget|
This white paper describes the Synopsys DesignWare® ARC® HS38 multicore processor for embedded Linux applications. The ARC HS38 processor is the latest addition to the ARC HS Family and adds several features including MMU, cache coherent symmetric multiprocessing and L2 cache. This whitepaper describes the key HS38 features for delivering high speed of operation with exceptional code density and power efficiency. Other topics covered include dual- and quad-core configurations, configurability options and instruction set architecture (ISA) extensibility that is unique to the ARCv2 architecture. This report was prepared by the Linley Group based on their analysis for the HS38 Processor.
Tom R. Halfhill, Senior Analyst, The Linley Group
|Ultra Low-Power 9D Sensor Fusion Implementation|
Today, the ability to track the orientation or position of a device is a common feature in many portable and wearable products. Computing the orientation is a non-trivial task that converts inputs from multiple motion sensors into accurate position information. This computation is called sensor fusion and it eliminates inaccuracies from noisy sensor inputs. This paper shows how to implement a power-efficient 9D fusion algorithm on an IP subsystem: a processor core that is augmented with hardware accelerators. This implementation makes it applicable in products that require low energy consumption.
Pieter Struik, R&D Engineer, Sr. Staff, Synopsys
|Building an Efficient, Tightly Coupled Embedded System Using an Extensible Processor|
The increasing demand for better filtering and processing capabilities of the processor within embedded systems results in a trend to shift from 8-bit microcontroller tightly coupled embedded systems towards 32-bit processor bus-based embedded systems. As a consequence, the power, performance and area (PPA) ratio of these systems also shifts in favor of performance at the cost of power and area. However ultra low power and small area are the main drivers for these embedded systems. This white paper describes how closely coupled memories and processor extensions can be leveraged to improve the power and area of these embedded systems by making the bus infrastructure superfluous.
Jeroen Geuzebroek, Sr. R&D Engineer, Synopsys; Ad Vaassen, Sr. System Engineer, Synopsys
|Leveraging Processor Extensibility to Build an Ultra Low-Power Embedded Subsystem|
The ever increasing demand for smaller electronic devices, with more functionality, longer battery life, and shorter time to market has accelerated use of embedded processors and subsystems to offload the host processor from commonly executed tasks. Processor extensions provide a means to extend a general-purpose processor with custom hardware accelerators to optimize the execution of dedicated applications for reduced energy consumption and area, and/or increased performance. This white paper describes how processor extensions can optimize power and performance of a processor when targeting sensor applications, demonstrated using Synopsys’ DesignWare® ARC® Processors and ARC Processor Extensions (APEX) technology.
Jeroen Geuzebroek, Senior R&D Engineer, Synopsys
|The Linley Group: Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications|
This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company’s newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features.
Tom R. Halfhill, Senior Analyst, The Linley Group; J. Scott Gardner, Senior Analyst, The Linley Group
|The Linley Group: DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications|
This paper describes Synopsys’ DesignWare® ARC® EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores.
J. Scott Gardner, Senior Analyst, The Linley Group; Tom R. Halfhill, Senior Analyst, The Linley Group
|The Rise of SIP Subsystems: What is the Value to Silicon Architects and SoC Designers|
The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i.e. subsystems). This whitepaper discusses how the use IP subsystems to reduce the level of effort designers must expend to create highly complex SoC designs will represent the future of the SoC development in the semiconductor industry.
Rich Wawrzyniak, Sr. Market Analyst: ASIC & SoC, Semico Research Corp
|Obfuscating Attacks on Secure SoCs through Encrypted Code Execution|
Security concerns continue to prevail in a wide variety and growing number of application areas for SoCs, with attacks commonly targeting memory contents and processor operation. Secure SoCs, such as those commonly found in payment cards, often come under various forms of attacks from hackers seeking to access the information stored in the on-chip memories and use it for illegal financial gain. As a result, security schemes must be varied and many, while limiting cost and performance impact. By enabling on-the-fly execution of encrypted code, the ARC Secure option for DesignWare ARC 600 processors ensures that attacks accessing instruction memory contents find encrypted code, and attacks focused on processor operational signatures (such as state or state changes) are more difficult to carry out.
Steve Tateosian, Synopsys, Inc., Product Marketing Manager
|Improving Performance and Simplifying Coding with XY Memory’s Implicit Parallelism|
Explicit and implicit instruction-level parallelism techniques boost processor performance by increasing the amount of work done in a given time interval. Implicit parallelism using XY memory retains the RISC programming model and brings all the XY memories into the pipeline, resulting in a resource-efficient and high-performing implementation. The DesignWare® ARC® XY Advanced DSP extension adds digital signal processing to the ARC processors, enabling RISC and signal processing computation within a single unified architecture.
Manny Wright, Senior FAE, Synopsys, Inc.
|High-End Audio Made Easy: The Software Story|
Audio requirements are soaring. Whereas audio used to be done in a few spare cycles of the main CPU, decoding today’s Blu-ray Disc 24-bit, 192 kHz high-definition audio streams, or post-processing 9.1 channel Pro Logic IIz streams, requires significant performance. An obvious solution is to offload the processing to one or more dedicated audio digital signal processors (DSPs) such as the DesignWare® ARC® AS211SFX/AS221BD Audio Processors, but this complicates system design and introduces a number of hardware and software challenges. This white paper elaborates on these challenges and presents a number of architectural solutions. In addition to the offloading complexities, this paper covers the integration of audio processing software in larger multimedia and product software stacks, by describing how to integrate audio software into popular Linux- and Android-based systems.
Ruud Derwig, Synopsys, Inc., Senior Staff
|Audio Subsystems for Efficient SoC Integration|
Implementing advanced audio functionality in a system-on-chip (SoC) involves integrating a range of hardware and software components, including an audio processor, audio peripherals, software drivers, and audio processing software. In this white paper, we discuss the requirements for audio solutions for processing of high-definition (HD) multi-channel audio and detail the challenges involved in building such solutions.
Pieter van der Wolf, Synopsys Inc., Senior Staff
|Reality Check: A Guide to Understanding Optimized Processor Cores|
The performance of the processor core in an SoC is often a key product differentiator. It's not just about performance though - power and cost are equally important considerations. In today's markets, SoC developers have to hit aggressive power, performance and area goals to remain competitive. This white paper discusses the many interacting parameters that determine the optimum implementation for your application.
Jonathan Young, Brian Machesney, Synopsys, Inc.