DesignWare USB IP Solutions

INTERNATIONAL| SOLVNET

Home

Interface and Standards IP

USB

DesignWare USB IP Solutions

Overview

Synopsys, an industry leader in USB Intellectual Property (IP) cores, provides a complete portfolio of high quality IP for designs requiring USB 1.1, 2.0 or 3.0. The Synopsys DesignWare USB IP solution helps your projects get to tape out on schedule and work on first silicon by providing a comprehensive USB offering including the digital core IP, verification IP and mixed-signal PHY IP.
PDF

USB Complete Solution Datasheet

Products

SuperSpeed USB
USB 3.0 IP solution with controllers, PHY, VIP, virtual platform and drivers more

The DesignWare® SuperSpeed USB IP complete solution is based on the USB 3.0 specification from the USB Implementers Forum and consists of the xHCI host and device controllers, PHY and verification IP.

USB 2.0 Controllers
Designed for single-chip, USB 2.0 integration in Device and Host applications more

	USB 2.0 LPM-HSIC	Implements a new power sleep state which reduces power consumption, by providing faster suspend and resume times by three orders of magnitude. DOWNLOAD DATASHEET

	USB 2.0 OTG	The IP performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 compliant peripheral or a USB 2.0 host DOWNLOAD DATASHEET

	USB 2.0 Host	Compliant with the specifications for the USB 2.0 Enhanced Host Controller Interface (EHCI) and the USB 1.1 Open Host Controller Interface (OHCI) 1.0. DOWNLOAD DATASHEET

	USB 2.0 Device	Compliant to the USB 2.0 specification. The IP supports high-speed (480-Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) devices and USB 2.0 UTMI DOWNLOAD DATASHEET

USB 2.0 PHYs
Designed for single-chip, USB 2.0 integration in Device and Host applications more

	USB 2.0 picoPHY	The USB 2.0 picoPHY supports the Battery Charging v1.1 and OTG 2.0 specifications, and is designed for low power and small area DOWNLOAD DATASHEET

	USB 2.0 nanoPHY	Compliant to the USB 2.0 specification. The USB 2.0 nanoPHY is targeted to leading 45nm, 65nm, 90nm, and 130nm low power CMOS digital logic processes DOWNLOAD DATASHEET

	USB 2.0 HSIC-LPM PHY	Compliant to the USB 2.0 specification. The IP supports 1.2V LVCMOS signaling with integrated PHY including transmitter, receiver, digital core, ESD & 480 Hz PLL DOWNLOAD DATASHEET

	USB 2.0 OTG PHY	Compliant to the USB 2.0 specification .The PHY IP includes all the required logical, geometric, & physical design files to implement USB 2.0 OTG capabilities

USB 1.1 Controllers
Compliant with revision 1.1 of the USB specification more

	USB 1.1 Host	The USB 1.1 Host is compliant with the USB 1.1 specification. The IP supports full and low speeds and is compatible with USB 2.0 & Open HCI 1.0 specifications area. DOWNLOAD DATASHEET

	USB 1.1 Device	The USB 1.1 Device is compliant with USB 1.1 specification. The IP supports full and low speeds devices.

	USB 1.1 Hub	The USB 1.1 Hub is compliant with USB 1.1 specification. The IP supports low-speed and full speed devices on downstream ports DOWNLOAD DATASHEET

USB 1.1 PHYs
Compliant USB 1.1 PHY for SoC integration in device and host applications more

USB 1.1 PHYs

The DesignWare USB 1.1 PHY transmits and receives serial data at both full-speed (12 Mbps) and low speed (1.5 Mbps) data transfer rates. The PHY is available in 90 nm, 130 nm and 180 nm processes
PDF