DesignWare USB IP Solutions

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DesignWare USB IP Solutions

Overview

Synopsys, an industry leader in USB Intellectual Property (IP) cores, provides a complete portfolio of high quality IP for designs requiring USB 1.1, 2.0 or On-The-Go (OTG). The Synopsys DesignWare USB IP solution helps your projects get to tape out on schedule and work on first silicon by providing a comprehensive USB offering including the digital core IP, verification IP and mixed-signal PHY IP.
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USB Complete Solution Datasheet

Products

SuperSpeed USB 3.0
USB 3.0 IP solution with controllers, PHY, VIP, virtual platform and drivers more

The DesignWare® SuperSpeed USB IP complete solution is based on the USB 3.0 specification from the USB Implementers Forum and consists of the xHCI host and device controllers, PHY and verification IP.

HS USB 2.0 LPM-HSIC
new power sleep state which reduces power consumption more

Implements a new power sleep state which reduces power consumption, by providing faster suspend and resume times by three orders of magnitude.
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HS USB 2.0 OTG
high-quality USB IP for the most demanding USB 2.0 peripherals more

The IP performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 compliant peripheral or a USB 2.0 host
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HS USB 2.0 Host
synthesizable building blocks used to implement a complete USB 2.0 host more

Compliant with the specifications for the USB 2.0 Enhanced Host Controller Interface (EHCI) and the USB 1.1 Open Host Controller Interface (OHCI) 1.0.
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HS USB 2.0 Device
supports high-speed, performing 40 times faster than USB 1.1 more

Compliant to the USB 2.0 specification. The IP supports high-speed (480-Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) devices and USB 2.0 UTMI
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HS USB 2.0 LPM-HSIC PHY
new power sleep state which reduces power consumption more

Compliant to the USB 2.0 specification. The IP supports 1.2V LVCMOS signaling with integrated PHY including transmitter, receiver, digital core, ESD & 480 Hz PLL
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HS USB 2.0 nanoPHY
half the power and die area for longer battery life and lower silicon cost more

Compliant to the USB 2.0 specification. The USB 2.0 nanoPHY is targeted to leading 45nm, 65nm, 90nm, and 130nm low power CMOS digital logic processes
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HS USB 2.0 OTG PHY
designed for single-chip, USB 2.0 integration in OTG applications more

Compliant to the USB 2.0 specification .The PHY IP includes all the required logical, geometric, & physical design files to implement USB 2.0 OTG capabilities

HS USB 2.0 PHY
designed for single-chip, USB 2.0 integration in Device and Host applications more

Compliant to the USB 2.0 specification. The PHY IP includes all the required logical, geometric, and physical design files to implement USB 2.0 capabilities
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USB 1.1 Host
runs at Full and Low Speeds and is compatible with USB 2.0 more

The USB 1.1 Host is compliant with the USB 1.1 specification. The IP supports full and low speeds and is compatible with USB 2.0 & Open HCI 1.0 specifications.
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