DesignWare Interface and Standards IP 

Complete Interface IP Solutions for the Most Popular Protocols 

Synopsys offers designers a broad portfolio of complete, silicon-proven IP solutions for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. With a strong investment in developing high quality IP, designers can trust that the IP will interoperate and integrate successfully into the SoC with less risk and improved time to market.

Thousands of customers trust DesignWare IP in their SoCs. See why Synopsys is their Trusted IP Partner.

  • Products
 
  • AMBA
  • Comprehensive IP solutions for AMBA 2.0, AMBA 3 AXI and AMBA 4 AXImore

Infrastructure/Fabric
The DesignWare IP solutions for the AMBA® interconnect includes synthesizable IP, verification IP and an automated method for subsystem assembly.


AHB DMA Controller
The highly optimized centralized AHB DMA Controller supports up to 8 channels each with dedicated channel buffers.


AXI DMA Controller
The highly optimized centralized AXI DMA Controller is configurable for up to 8 channels for a range of applications.


APB General Peripheral
The highly configurable APB general peripherals provide designers with the flexibility to tailor the components to the desired design requirements.


APB Advanced Peripheral
The highly configurable APB Advanced Peripheral provide designers with the flexibility to tailor the components to their desired design requirements


Verification IP
AMBA VIP includes support for AMBA AXI4, ACE, AXI3 AHB and APB. It is based on Synopsys’ SystemVerilog UVM architecture and supports all popular simulators.

  • DDR
  • Complete DDR4/3/2 and LPDDR4/3/2 IP solutions for up to 3200 Mbps more

DDR Complete Solution
Complete DDR IP solution consisting of protocol and memory controllers, PHY IP, and Verification IP
PDF DOWNLOAD DATASHEET


Enhanced Universal DDR Controllers
DDR memory and protocol controller IP supporting DDR4, DDR3/3L/3U, DDR2, Mobile DDR, LPDDR4, LPDDR3, and LPDDR2
PDF DOWNLOAD DATASHEET


Basic Universal DDR Controllers
DDR memory and protocol controller IP supporting DDR3/3L/3U, DDR2, Mobile DDR, LPDDR, and LPDDR2
PDF DOWNLOAD DATASHEET


DDR4/3 PHY
Supports DDR4/DDR3/DDR3L up to 3200 Mbps with embedded calibration processor
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DDR4 multiPHY
Supports DDR4 and DDR3/3L/3U up to 2667 Mbps and LPDDR3/2 up to 2133  Mbps
PDF DOWNLOAD DATASHEET


LPDDR4 multiPHY
Supports LPDDR4, LPDDR3, DDR4, DDR3/3L/3U SDRAMs up to 3200 Mbps
PDF DOWNLOAD DATASHEET


Gen 2 DDR multiPHY
Supports LPDDR3/2 up to 2133 Mbps and DDR3/3L/3U up to 2133 Mbps
PDF DOWNLOAD DATASHEET


DDR multiPHY
Supports LPDDR2, Mobile DDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF DOWNLOAD DATASHEET


DDR3/2 SDRAM PHY
Supports DDR3/3L and DDR2 up to 2133 Mbps
PDF DOWNLOAD DATASHEET


DDR2/3-Lite/mDDR SDRAM PHY
Supports DDR3, DDR2 and LPDDR up to 1066 Mbps
PDF DOWNLOAD DATASHEET


IP Prototyping Kits
Accelerate DDR3 and LPDDR3/2 IP development with reference designs and a HAPS-DX FPGA-based prototyping system
PDF DOWNLOAD DATASHEET (PDF)

  • Ethernet
  • Comprehensive silicon-proven, compliant Ethernet solutionsmore

Enterprise MAC IP
High-performance, energy-efficient, configurable 1G/10G/25G/40G/50G/100G Ethernet MAC IP compliant with the IEEE 802 and consortium specifications
PDF DOWNLOAD DATASHEET (PDF)


Ethernet XGMAC IP
Configurable 1G/2.5G/5G/10G Ethernet XGMAC IP compliant with the IEEE 802 and consortium specifications
PDF DOWNLOAD DATASHEET (PDF)


Ethernet GMAC IP
Configurable 10/100/1G Universal MAC controller IP compliant with the IEEE 802 specifications, composed of the GMAC, MTL, and MDC
PDF DOWNLOAD DATASHEET (PDF)


Ethernet MAC IP
Configurable 10/100 Universal MAC controller IP compliant with the IEEE specifications composed of the GMAC, MTL, and MDC
PDF DOWNLOAD DATASHEET (PDF)


Enterprise PCS IP
High-performance, energy-efficient, configurable 1G/10G/25G/40G/50G/100G Ethernet PCS IP compliant with the IEEE 802 and consortium specifications
PDF DOWNLOAD DATASHEET (PDF)


Ethernet PCS IP
High-performance, energy-efficient, configurable 1G/2.5G/5G/10G Ethernet PCS controller IP compliant with the IEEE 802 and consortium specifications
PDF DOWNLOAD DATASHEET (PDF)


Ethernet Quality-of-Service IP
Configurable 10M/100M/1G MAC IP compliant with the multiple IEEE specifications and ASIL B Ready certified IP associated with Time Sensitive Ethernet applications.
PDF DOWNLOAD DATASHEET (PDF)


Multi-Protocol 16G PHY IP
1.25-16 Gbps PHY for Ethernet 40/10GBASE-KR/KR4, 10GBASE-KX4/XAUI, 1000BASE-KX/SGMII and more
PDF DOWNLOAD DATASHEET (PDF)


Multi-Protocol 12G PHY IP
1.25-12.5 Gbps PHY for Ethernet 40/10GBASE-KR/KR4, 10GBASE-KX4/XAUI, 1000BASE-KX/SGMII and more
PDF DOWNLOAD DATASHEET (PDF)


XAUI PHY IP
PHY IP supports the 10G Ethernet standards in a wide range of process technologies
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate Ethernet IP prototyping, software development and integration
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
Verification of 10M/100M/1G up to 100G MAC and PHY interfaces
PDF DOWNLOAD DATASHEET (PDF)

  • HDMI
  • Silicon-proven HDMI 2.0, 1.4 and 1.3 TX & RX solution: Controller and PHYmore

HDMI 2.0 Transmitter (TX)
The HDMI 2.0 TX interface comprises Controller IP, PHY IP, software, and Linux drivers to perform the serialization and transmission of audio, video, and control information.
PDF DOWNLOAD DATASHEET


HDMI 2.0 Receiver (RX)
The HDMI 2.0 RX interface comprises Controller IP, PHY IP, software, and Linux drivers to perform the serialization and reception of audio, video, and control information.
PDF DOWNLOAD DATASHEET


HDMI 1.4 Transmitter (TX)
The HDMI 1.4 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through and HDMI interface.
PDF DOWNLOAD DATASHEET


HDMI 1.4 Receiver (RX)
The HDMI 1.4 RX interface compromises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
PDF DOWNLOAD DATASHEET


HDMI 1.3 Transmitter (TX)
The HDMI 1.3 TX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
PDF DOWNLOAD DATASHEET


HDMI 1.3 Receiver (RX)
The HDMI 1.3 RX interface comprises of Controller and PHY to perform the serialization and transmission of video, audio and control information through an HDMI interface.
PDF DOWNLOAD DATASHEET


IP Prototyping Kits
Accelerate HDMI IP prototyping, software development and integration


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET


Verification IP
Rapid verification of HDMI 2.0, 1.4, 1.3 interfaces
PDF DOWNLOAD DATASHEET

  • JPEG
  • Multimedia IP solution for image compression and decompressionmore

 
The CODEC encodes and decodes still or motion image data of up to four color components, according to the JPEG baseline algorithm as specified in the ISO/IEC 10918-1 standard.
PDF DOWNLOAD DATASHEET

  • MIPI
  • Comprehensive silicon-proven MIPI IP solutionsmore

CSI-2 Controller IP
Synthesizable host and device controllers for high-speed serial interface between an application or image processor and camera sensors


DSI Controller IP
Synthesizable host and device controllers for high-speed serial interface between an application processor and displays


I3C Controller IP
Controller IP delivers high bandwidth and scalability for integration of multiple sensors
PDF DOWNLOAD DATASHEET (PDF)


UFS Host Controller IP
High-performance serial interface IP compliant with the latest Universal Flash Storage (UFS), UFS Host Controller Interface (UFSHCI) specifications and UFS card
PDF DOWNLOAD DATASHEET (PDF)


UniPro Controller IP
Configurable, synthesizable controller IP for JEDEC UFS, MIPI CSI-3 and Google ARA UniPort-M specifications
PDF DOWNLOAD DATASHEET (PDF)


SD/eMMC Host Controller IP
High-performance, low-power controller IP compliant with the latest SD, SDIO and eMMC specifications
PDF DOWNLOAD DATASHEET (PDF)


D-PHY IP
High-performance, low-power PHY IP available in advanced process technologies
PDF DOWNLOAD DATASHEET (PDF)


M-PHY IP
Silicon-proven, low-power PHY IP with support for high-speed Gear 3 rates available in advanced process technologies
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate MIPI DSI and CSI-2 IP as well as JEDEC UFS IP prototyping, software development and integration


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
Verification of MIPI as well as UFS, SD and eMMC interfaces


UFS Host Controller IP
High-performance serial interface IP for the Universal Flash Storage (UFS), UFS Host Controller Interface (UFSHCI) specifications and UFS card
PDF DOWNLOAD DATASHEET


UniPro Controller IP
Configurable, synthesizable controller IP for JEDEC UFS, MIPI CSI-3 and Google ARA UniPort-M specifications
PDF DOWNLOAD DATASHEET


SD/eMMC Host Controller IP
High-performance, low-power controller IP for SD, SDIO and eMMC specifications
PDF DOWNLOAD DATASHEET


M-PHY IP
Silicon-proven, low-power PHY IP with support for high-speed Gear 3 rates available in advanced process technologies
PDF DOWNLOAD DATASHEET


IP Prototyping Kits
Accelerate UFS IP prototyping, software development and integration
PDF DOWNLOAD DATASHEET (PDF)


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Verification IP
Verification of UFSeMMCSD and MIPI M-PHY interfaces


Multi-Protocol 16G PHY IP
1.25-16 Gbps PHY for PCIe 4.0, SATA 6G, Ethernet 40/10GBASE-KR/KR4, 10GBASE-KX4/XAUI, 1000BASE-KX/SGMII and more
PDF DOWNLOAD DATASHEET


Multi-Protocol 12G PHY IP
1.25-12.5 Gbps PHY for PCIe 3.1, SATA 6G, Ethernet 40/10GBASE-KR/KR4, 10GBASE-KX4/XAUI, 1000BASE-KX/SGMII and more
PDF DOWNLOAD DATASHEET


Multi-Protocol 8G PHY IP
1.5-8.0 Gbps for PCIe 3.1, SATA 6G
PDF DOWNLOAD DATASHEET (PDF)

  • PCI Express
  • Complete, silicon-proven PCI Express 4.0, 3.1, 2.1, and 1.1 IP solutionsmore

Endpoint IP
Implements the port logic required for a PCIe Endpoint and supports the PCIe 4.0, 3.1, 2.1, and 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET


Root Port IP
Implements the port logic required for a PCIe Root Complex and supports the PCIe 4.0, 3.1, 2.1, and 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET


Dual Mode IP
Implements the port logic required for both a PCIe Root Complex and Endpoint and supports the PCIe 4.0, 3.1, 2.1, and 1.1 and PCI-SIG SR-IOV specifications
PDF DOWNLOAD DATASHEET


Switch Port IP
Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and supports the PCIe 4.0, 3.1, 2.1, and 1.1 specifications
PDF DOWNLOAD DATASHEET


PCI Express to AHB Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 2.0 AHB on-chip bus
PDF DOWNLOAD DATASHEET


PCI Express to AXI Bridge
Allows the DesignWare PCIe port logic to bridge to the AMBA 3 AXI/4 AXI on-chip bus
PDF DOWNLOAD DATASHEET


Single Root I/O Virtualization IP
Integrates quickly, easily into SoC designs with a user-friendly application interface and conservative timing for a wide range of ASIC and FPGA technologies
PDF DOWNLOAD DATASHEET (PDF)


PCIe 4.0 PHY IP
Multi-channel, high-performance PCIe PHY IP operating at 16 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


PCIe 3.1 PHY IP
Multi-channel, low-power PCIe PHY IP operating at 8 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


PCIe 2.1 PHY IP
Multi-channel, low BOM cost PCIe PHY IP operating at 5 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


PCIe 1.1 PHY IP
Multi-channel PCIe PHY IP operating at 2.5 Gbps available for numerous processes and foundries
PDF DOWNLOAD DATASHEET (PDF)


M-PCIe IP
Scalable controller IP that implements the port logic required to build a Root Port, Endpoint, Dual Mode, or Switch device
PDF DOWNLOAD DATASHEET (PDF)


IP Prototyping Kits
Accelerate PCIe IP prototyping, software development and integration


IP Virtualizer Development Kits
Software development kits for early software bring-up, debug and test


Interface IP Subsystems
Configurable, pre-verified IP solutions for rapid SoC integration
PDF DOWNLOAD DATASHEET (PDF)


Verification IP
VC VIP for PCIe acts as either a Root Complex or Endpoint with support for PCIe 4.0, 3.1, 2.1, 1.1, PIPE, SerDes, all popular simulators and M-PHY; It includes optional source-based test suites and support for NVMe
PDF DOWNLOAD DATASHEET (PDF)


PCI
The PCI IP supports 32-bit or 64-bit bus paths on either the PCI bus or the application interface and is compliant with the PCI 2.3 specification.
PDF DOWNLOAD DATASHEET


PCI-X
The IP supports 32-bit or 64-bit PCI-X bus paths and is compliant with the PCI-X 2.0 (mode1) also know as 1.0a and the PCI 2.3 specifications.
PDF DOWNLOAD DATASHEET

  • SATA
  • Complete, interoperable SATA IP Solution: Device, Host, PHY, VIPmore

SATA Complete Solution
Comprehensive SATA IP solution consisting of host, device, PHY and Verification IP.
PDF DOWNLOAD DATASHEET


Enterprise 12G PHY
Silicon-proven PHY supporting SATA 6G
PDF DOWNLOAD DATASHEET


SATA PHY
Low in power consumption and area, the PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity
PDF DOWNLOAD DATASHEET


Verification IP
Synopsys SATA VIP can act as a device or a host and includes support for SATA Gen1, Gen2 and Gen3 with speeds up to 6GB. It supports all popular simulators.
PDF DOWNLOAD DATASHEET

  • USB
  • Complete, silicon-proven USB IP solution: controller, PHY and VIPmore

USB Complete Solution
Complete USB IP solution including controllers, PHY IP, Verification IP, IP Prototyping Kits and IP software development kits for USB Type-C, USB 3.1, USB 3.0, SSIC, HSIC, USB 2.0, LPM-HSIC and more
PDF DOWNLOAD DATASHEET


USB-C 3.1/DisplayPort 1.3 TX IP
USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers with HDCP 2.2 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
PDF DOWNLOAD DATASHEET


USB-C/USB 3.1 PHY
USB-C 3.1 (with Type-C support) and USB 3.1 PHY IP for SoC integration in Device and Host applications
PDF DOWNLOAD DATASHEET


USB 3.1 Controllers
Device, xHCI Host and Dual-Role Device controller IP
PDF DOWNLOAD DATASHEET


USB 3.0 Dual-Role Device
USB 3.0-compliant IP for Device- and Host-side applications. Supports SuperSpeed, High-Speed, Full Speed and Low Speed implementations as well as SSIC, HSIC and OTG


USB 3.0 xHCI Host
USB 3.0-compliant IP for Host-side applications. Supports SuperSpeed, High Speed, Full Speed and Low Speed implementations as well as SSIC and HSIC


USB 3.0 Device
USB 3.0-compliant IP for Device-side applications. Supports SuperSpeed and High-Speed implementations as well as SSIC and HSIC


USB-C/USB 3.0 PHY
USB-C 3.0 (with Type-C support) and USB 3.0 PHY IP for SoC integration in Device and Host applications


USB-C/USB 3.0 femtoPHY
Supports complete USB 3.0 implementation (SuperSpeed, High Speed, Full Speed, and Low Speed) in a 50% smaller footprint than the standard USB 3.0 PHY
PDF DOWNLOAD DATASHEET


USB Type-C 2.0 Solution for IoT
Controllers and PHYs optimized for cost-sensitive and energy-efficient IoT edge applications.
PDF DOWNLOAD DATASHEET (PDF)


USB 2.0 HS OTG
The IP performs as a standard Hi-Speed Dual-Role Device (DRD), operating as either a USB 2.0 compliant peripheral or a USB 2.0 host
PDF DOWNLOAD DATASHEET


USB 2.0 EHCI Host
Compliant with the specifications for the USB 2.0 Enhanced Host Controller Interface (EHCI) and the USB 1.1 Open Host Controller Interface (OHCI) 1.0
PDF DOWNLOAD DATASHEET


USB 2.0 Device
Compliant to the USB 2.0 specification. The IP supports high-speed (480-Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) devices and USB 2.0 UTMI
PDF DOWNLOAD DATASHEET


USB 2.0 PHY
USB 2.0 PHY IP with Type-C support for Device & Host applications


USB 2.0 femtoPHY
Supports Type-C connectivity and complete USB 2.0 implementation (High-Speed, Full Speed and Low Speed) in a 50% smaller footprint than the standard USB 2.0 PHY
PDF DOWNLOAD DATASHEET


USB 2.0 picoPHY
Designed for low power and small area, USB 2.0 picoPHY supports Type-C connectivity, Battery Charging v1.1, and OTG 2.0 specifications
PDF DOWNLOAD DATASHEET


USB 2.0 nanoPHY
Compliant to the USB 2.0 specification. The USB 2.0 nanoPHY is targeted to leading 45nm, 55nm, and 65nm low power digital logic processes
PDF DOWNLOAD DATASHEET


USB 2.0 LPM-HSIC PHY
Compliant to the USB 2.0 specification. The IP supports 1.2V LVCMOS signaling with integrated PHY including transmitter, receiver, digital core, ESD & 480 Hz PLL
PDF DOWNLOAD DATASHEET


USB 1.1 Host
The USB 1.1 Host is compliant with the USB 1.1 specification. The IP supports full and low speeds and is compatible with USB 2.0 & Open HCI 1.0 specifications.
PDF DOWNLOAD DATASHEET


USB 1.1 Device
The USB 1.1 Device is compliant with USB 1.1 specification. The IP supports full and low speeds devices.


USB 1.1 Hub
The USB 1.1 Hub is compliant with USB 1.1 specification. The IP supports low-speed and full speed devices on downstream ports
PDF DOWNLOAD DATASHEET


IP Prototyping Kits
Accelerate USB 3.1 and USB 3.0 IP development with reference designs and a HAPS-DX FPGA-based prototyping system


Verification IP
USB VIP supports USB 3.1, 3.0, 2.0 and OTG. It can act as a host, device or hub. It is based on Synopsys' SystemVerilog UVM architecture and supports all popular simulators.
PDF DOWNLOAD DATASHEET


 
Includes proven reference designs preloaded onto a HAPS-DX prototyping system, a PHY daughter board and a virtual or physical software development platform running Linux OS and reference drivers


 
Includes configurable models of DesignWare IP as part of a multi-core ARM Cortex-A57 reference design running Linux and reference drivers


 
Accelerate SoC development using configurable and customizable subsystems to reduce risk and improve time-to-market



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