Make it EASY with DesignWare DDR Hard PHY IP 

Synopsys DesignWare DDR PHYs are offered as "hard IP" meaning the PHY deliverables are primarily GDSII chip layout and the associated support material such as lef/lib/Verilog/LVS netlist, etc. This is in contrast to other DDR PHYs that are "soft IP" where the PHY is delivered as RTL and the customer must synthesize the "soft PHY", possibly including other third party DLLs and/or PLLs and close timing. The timing closure problems with soft PHYs become more onerous as the frequency of the DDR interface increases.

Make it EASY with Synopsys DesignWare DDR HARD PHY IP
  • Quicker integration
  • Easier timing closure
  • Better performance
  • Less silicon area
  • All IP supplied by one IP vendor
  • Hard DDR PHYs include I/Os
  • Hard PHYs have lower jitter, better duty cycle and an overall superior clock strategy
  • Hard PHYs use identical circuits for every bit of the parallel DDR interface reducing skew
  • Hard PHYs implemented in test chips are equivalent to the customer's PHY - Soft PHYs are different GDSII every time

All Synopsys DDR PHYs also include the application specific DDR I/Os that are required for a complete contiguous I/O ring for the DDR PHY. The unique DDR PHY approach from Synopsys allows complete flexibility of the I/O ring layout to balance the I/O ring for small area and good signal integrity. Soft DDR PHYs require that the I/Os be acquired from some other third party IP supplier meaning that as many as 5 different IP vendors can be involved in a soft PHY implementation whereas everything you need for a complete DDR interface can be acquired from Synopsys.

Unlike soft PHY solutions, the DesignWare DDR PHYs hard macro incorporates analog DLL or PLL circuits which enable lower jitter, better duty cycle and an overall superior clock strategy. While soft PHYs often spend over a month on design iterations to close timing and have lower operating frequency ceilings, hard PHYs allow designers to easily meet timing closure and high performance targets, helping to significantly ease the SoC integration effort. As hard IP, a DesignWare DDR PHY embeds the high-speed clock tree and flight time matched data buses, resulting in a more area efficient and lower power design.

DesignWare DDR3/2 IP Demo at 1600 Mbps
Live from DesignCon 2010, see how the DesignWare DDR3/2 IP enables automatic timing compensation for voltage and temperature changes, per bit deskew adjustments in the datapath, and on-chip capabilities for measuring write and read data eyes.
Graham Allan, Product Marketing Manager, Memory Interface IP; Vishal Thareja, Test Engineer

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