New DesignWare USB 2.0 and 3.0 femtoPHY IP 

Cut USB PHY Area by 50% with DesignWare USB 2.0 & 3.0 femtoPHY IP

Proven in customer silicon on 28-nm and FinFET processes, the Synopsys DesignWare® USB 3.0 femtoPHY IP and DesignWare USB 2.0 femtoPHY IP provides designers with a complete PHY IP solution for low-power mobile and consumer applications such as smartphones, tablets, digital TVs, and networking applications. Offering reduced silicon cost and longer battery life, the DesignWare USB femtoPHY IP delivers up to 50% smaller die area than previous generations and minimizes power consumption.

Synopsys developed the USB 3.0 and 2.0 femtoPHY IP to enable designers to select the optimal implementation for their application without sacrificing the features or capabilities required for USB compliance certification, and both femtoPHYs have passed USB-IF compliance testing. Whether taking advantage of the USB 3.0 femtoPHY’s 5.0 Gbps data transfer rates or the USB 2.0 femtoPHY’s 480 MHz data transfer rates, both DesignWare USB femtoPHYs minimize the number of pins needed on the SoC periphery to reduce SoC area and cost. Power down features minimize battery drain when the PHY is inactive, while retaining all PHY states to enable fast, accurate power-on capabilities. In addition, the DesignWare USB femtoPHYs support the popular USB Battery Charging v1.2 specification and the USB On-The-Go (OTG) protocol.

The DesignWare USB femtoPHY builds on years of customer success with Synopsys’ silicon-proven USB PHY IP product line, which has been ported to over 100 process nodes and configuration combinations ranging from 180-nm to 14/16-nm FinFET. When combined with the DesignWare USB digital controllers and verification IP, the DesignWare USB femtoPHY IP delivers a complete low power and small die area solution for advanced SoC designs.

New DesignWare® USB 3.0 & 2.0 femtoPHY IP: FinFET Silicon Success

View the silicon test results of the new DesignWare USB femtoPHY family. DesignWare USB 3.0 and 2.0 femtoPHYs, available now on leading FinFET process technologies, reduce USB area by 50% compared to previous generations.

Gervais Fong
Sr. Product Marketing Manager, USB IP

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