DesignWare minPower Components 

 

Today’s conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines. The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable DC Ultra™ to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications. Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption. In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable blocks that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.

testDesignWare minPower Components Datasheet

By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic. The table below shows the overall improvements in area and power in datapath circuits as recorded from initial customers designing wireless connectivity and high-performance networking applications. While the total chip power reduction achieved with the DesignWare minPower Components will vary, initial customers have reported design power reductions ranging from 2 to 20 percent in tested modes.

DesignWare minPower Components


 
  • Innovative low power datapath architectures with lower switchings and glitches
  • Configured automatically by DC Ultra for most fitted implementation based on power costing and switch activities or transition probabilities
  • Smart architecture generation for lower leakage cell mapping
  • Integrated datapath gating within datapath blocks eliminates the timing overhead resulted from inserted isolation gates
  • Instantiated IP with enhanced clock gating and built-in isolation logic for better dynamic power
  • New data tracking IP reduce dynamic power consumption for pipelined architectures
  • Extend battery life for mobile applications by lowering the power consumption for circuits with extensive active times
  • Reduce power consumption for high-performance computing circuits


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