South Asia 

For fastest support, please Open a Case online.

Singapore

Synopsys (Singapore) Private Limited
(Asia Pacific Headquarters & South Asia Sales Office)
300 Beach Road, #31-02
The Concourse
Singapore 199555
Tel: +65-6296-7433
Fax: +65-6297-1272
Email: sgp_feedback@synopsys.com

Malaysia

Malaysian Distributor, Trans-Dist Engineering
Blok C-T01-U04,
Jalan P8C-1, Presint 8,
62250 Putrajaya, Malaysia
Tel: +6-03-8888-9908
Fax: +6-03-8888-9909
Email: tde@tdesb.po.my

Workshop Schedule: 2013 to 2014

Date	Workshop	Cost
1-3 Apr 13	SystemVerilog Verification using UVM	US$1950
8-10 Apr 13	IC Compiler 1	US$1950
11 Apr 13	IC Compiler 2 CT	US$650
12 Apr 13	IC Compiler 2 HDP	US$650
15-17 Apr 13	PrimeTime 1	US$1950
18 Apr 13	PrimeTime Debugging	US$650
19 Apr 13	PrimeTime PX	US$650
22-24 Apr 13	Design Compiler 1	US$1950
29-30 Apr 13	HSIM	US$1300
2-3 May 13	HSPICE Essential	US$1300
6-7 May 13	Low Power Flow HLD	US$1300
8 May 13	Low Power Flow PnR	US$650
13-15 May 13	Design Compiler 1	US$1950
3-5 Jun 13	IC Validator	US$1950
17-19 Jun 13	DFT Compiler 1	US$1950
20-21 Jun 13	TetraMAX 1	US$1300
26-28 Jun 13	Design Compiler 1	US$1950
1-2 Jul 13	Low Power Flow HLD	US$1300
3 Jul 13	Low Power Flow PnR	US$650
8-10 Jul 13	Custom Designer	US$1950
15-17 Jul 13	IC Compiler 1	US$1950
18 Jul 13	IC Compiler 2 CT	US$650
19 Jul 13	IC Compiler 2 HDP	US$650
22-24 Jul 13	PrimeTime 1	US$1950
25 Jul 13	PrimeTime Debugging	US$650
26 Jul 13	PrimeTime PX	US$650
29-31 Jul 13	Design Compiler 1	US$1950
1-2 Aug 13	HSIM	US$1300
19-21 Aug 13	System Verilog for TestBench	US$1950
28-30 Aug 13	Design Compiler 1	US$1950
4-6 Sep 13	SystemVerilog Verification using UVM	US$1950
11-12 Sep 13	Low Power Flow HLD	US$1300
13 Sep 13	Low Power Flow PnR	US$650
16-18 Sep 13	DFT Compiler 1	US$1950
19-20 Sep 13	TetraMAX 1	US$1300
23-24 Sep 13	HSPICE Essential	US$1300
25-27 Sep 13	Design Compiler 1	US$1950
7-9 Oct 13	IC Compiler 1	US$1950
10 Oct 13	IC Compiler 2 CT	US$650
11 Oct 13	IC Compiler 2 HDP	US$650
16-18 Oct 13	IC Validator	US$1950
21-23 Oct 13	PrimeTime 1	US$1950
24 Oct 13	PrimeTime Debugging	US$650
25 Oct 13	PrimeTime PX	US$650
28-30 Oct 13	Design Compiler 1	US$1950
6-8 Nov 13	System Verilog for TestBench	US$1950
11-13 Nov 13	Custom Designer	US$1950
18-19 Nov 13	Low Power Flow HLD	US$1300
20 Nov 13	Low Power Flow PnR	US$650
27-29 Nov 13	Design Compiler 1	US$1950
2-3 Dec 13	Low Power Flow HLD	US$1300
4 Dec 13	Low Power Flow PnR	US$650
9-11 Dec 13	DFT Compiler 1	US$1950
12-13 Dec 13	TetraMAX 1	US$1300
18-20 Dec 13	Design Compiler 1	US$1950
30-31 Dec13	HSIM	US$1300
6-8 Jan 14	IC Compiler 1	US$1950
9 Jan 14	IC Compiler 2 CT	US$650
10 Jan 14	IC Compiler 2 HDP	US$650
13-15 Jan 14	PrimeTime 1	US$1950
16 Jan 14	PrimeTime Debugging	US$650
17 Jan 14	PrimeTime PX	US$650
20-22 Jan 14	Design Compiler 1	US$1950

** Synopsys reserves the right to cancel or re-schedule the workshops **
** Cancelled workshop

Please go to http://inter.viewcentral.com/reg/Synopsys/search and select the course listed in the table for course details.
Daily Class Time: 9.00am - 5.00pm

Advance Scheduling Workshop

Note: The following workshops require advanced scheduling and please contact sgp_training@synopsys.com for scheduling information:

Astro XTalk CATS Formality Hercules Nanosim Physical Compiler Power Cmpiler

PrimeTime SI Star-RCXT TCAD Vera

Registration

City: Singapore
Please click here for traning schedule and online registration.
Email: Singapore_training@synopsys.com for enquiry.

Direction map to education center (PDF)