Synopsys Insight 

2009 Past Issues   

Issue 4 - 2009
- The New Economics of Verification
- Parasitic Extraction for Next-generation Custom IC Design
- Using MATLAB and High-Level Synthesis for DSP Implementation

- SoC BENCHMARK: SoC Benchmark

Issue 3 - 2009
- New Technology Reduces Total Cost of Design
- Collaborating for Success at 32/28nm
- Coping with Modern AMS Verification Challenges
- In-Design Physical Verification

- SoC BENCHMARK: SoC Benchmark

Issue 2 - 2009
- IC Design: Rethink Recover
- Building Productive and Predictable Design Flows
- Using Parallelism to Double Simulation Speed
- SNUG 2009 Draws Record Crowds
- See Synopsys at DAC 2009

- SoC BENCHMARK: SoC Benchmark

Issue 1 - 2009
- The Next Era of Rapid Prototyping
- Simulating Solar Cells with TCAD
- A Methodology for Low Power Verification
- From Transaction Level to RTL
- Synopsys User's Group (SNUG) Israel 2009

- SoC BENCHMARK: SoC Benchmark


  © 2013 Synopsys, Inc. All Rights Reserved.
Contact us  |  Locations  |   Privacy  |  Legal   RSS   Twitter   LinkedIn   Facebook   YouTube