Synopsys Insight 

2006 Past Issues  
November, 2006
- The Value of Collaboration in Verification
- For SoCs, Size Matters
- Delivering Low-Power and DFM for 90-Nanometer Designs
- picoChip: From Startup to Success

Regional Focus
- Taiwan: Technology Leads the Road to Success
- Chinese Edition of ‘A Practical Guide for SystemVerilog Assertions’
- Synopsys China at ICCAD
- Synopsys Delivers Successful Professors’ Lecture Tour across China

- SoC BENCHMARK: Wide adoption of SystemVerilog to increase in 2007


October, 2006
- Designing Winning Products
- Improving Physical Design with IC Compiler
- Bringing DFM into Design
- Enhancing Performance, Power and Yield
- Moving to the Next Level in Verification Productivity and Predictability

Regional Focus - Europe
- New Architectures for the HSDPA Handset Revolution
- Mitigating Risk for Startups
- Meet the CEO - Interview with Aart De Geus, Synopsys

- SoC BENCHMARK: Process Technology Adoption


August - September, 2006
- Functional Verification from a Manager's Perspective
- Power Planning for SoCs
- Enhancing Synthesis Predictability and Productivity
- Synopsys Technology 'Sizzles' at DAC 2006

Regional Focus - Asia
- Customer Spotlight: Renesas Design Viet Nam Targets Gate and Headcount Growth
- Customer Spotlight: Sunplus Technology Realize Aggressive Cost and Schedule Goals
- Synopsys in Asia: Synopsys Launches Website for China
- Industry Insight: Synopsys Taiwan Celebrates 15 Years of Growth

- SoC BENCHMARK: Gate Count Trends


June - July, 2006
- Implementation – Complete, Correlated and Concurrent
- A Practical Methodology Calculates IR Drop Targets for SoCs
- Transaction-Level Modeling: SystemC or SystemVerilog?
- High Definition TV Design

Regional Focus - India
- Industry Focus: The Three Ps: Key Characteristics for Success
- Community Relations:Synopsys India and the Community

- SoC BENCHMARK: Chip performance trends


May, 2006
- The Three Ps: Key Characteristics for Success
- DesignWare Verification IP Support for VMM
- Synopsys Aligns with India's Strong Semiconductor Growth

April, 2006
- Certified Wireless USB Adoption
- The Economics of Scan Test Compression
- Low Power USB 2.0 PHY IP for High Volume Consumer Applications
- SystemVerilog: Complete Flow

February - March, 2006
- Improving System Reliability Using the Saber® Simulator in a Robust Design Flow
- Redefining High Definition by Design
- Synopsys 2006 Seminars

January, 2006
- A Blueprint for SoC Verification Success with SystemVerilog
- Integrating DFM in the Design Flow