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Issue 4, 2012
Synopsys Innovation Update
Latest News on Product, Technologies, Services and Solutions to Help Accelerate Innovation
Synopsys offers a wide range of products, solutions, and services to the global electronics market for designing and manufacturing semiconductors. In this article, we provide a brief overview of key additions to some of our existing solutions as well as showcase recent innovations to Synopsys' ever-growing lineup of software, IP and services.
Figure 1: The Synopsys product portfolio spans from Systems to SoC to Silicon.
The HAPS family of products provides an integrated and scalable hardware-software solution leveraged by design and validation teams to improve their ASIC design schedules and avoid costly device re-spins. Synopsys has developed its sixth-generation HAPS-70 FPGA-based prototyping environment to be more flexible and reusable than other prototyping systems featuring a new modular system architecture with support for up to 144 million ASIC gates and 3x higher in system prototype performance compared to roll-your-own solutions.
Read the full article on HAPS-70 in this issue of Insight.
Learn more about the HAPS Family of FPGA-Based Prototyping Solutions.
|Functional Verification Solution|
The Synopsys suite of Functional Verification solutions are tightly integrated, best-in-class technologies that allow designers to find bugs quickly and easily, significantly improving the quality of the most complex designs and enabling first-pass silicon success. These tools include VCS®, the functional verification solution used by leading SoC teams; Verdi, the industry's de facto debug platform for design and verification; ZeBu, the industry's performance and capacity leader in emulation; Discovery™ Verification IP, the industry's next-generation VIP; MVSIM and MVRC for multi-voltage native low-power simulation and low-power rule checking; Hector, an innovative formal block-level consistency checking solution; Magellan, the formal hybrid verification solution; and the Leda static checking solution.
Learn more about Functional Verification.
Discovery™ VIP for ARM® AMBA® 4 AXI4™
Discovery Verification IP (VIP) is a next-generation VIP written entirely in SystemVerilog and based on the proven VIPER Architecture to deliver greater performance, protocol-aware debug, coverage, ease-of-use and extensibility to speed and simplify the verification of the most complex protocols and system-on-chip (SoC) designs. With the recent release for ARM® AMBA® 4 AXI4™ protocol, Discovery VIP now offers a Performance Checker capability enabling system-on-chip (SoC) verification teams to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks.
Learn more about Discovery VIP.
Discovery™ VIP for Ethernet
Discovery Verification IP (VIP) for Ethernet, with support for 10/100 1G, 10G, 40G and 100G interfaces, will be released in December 2012. Discovery VIP for Ethernet builds on a proven foundation of Ethernet VIP with additional features provided by the next-generation VIPER architecture for high productivity and improved testbench methodology support. Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification webinar will be broadcasted on December 11, 2012.
View the webinar.
Learn more about Discovery VIP.
|DesignWare® STAR Memory System®|
The DesignWare STAR Memory System is an automated pre- and post-silicon memory test, debug, diagnostic and repair solution that enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. Targeting 20-nm and FinFET-based designs, the latest release includes advanced test algorithms and a new architecture enabling hierarchical implementation and validation of large SoC designs containing thousands of embedded memories, which can decrease the time required to implement tests while also reducing area by as much as 30 percent.
Read the full press release.
Learn more about the STAR Memory System.
|Lynx – Adaptive Resource Optimizer|
Adaptive Resource Optimizer (ARO) is a compute farm optimization feature in Synopsys' Lynx Design System. ARO monitors usage patterns of submitted jobs and determines a more optimal value to be used for reserving compute resources (e.g., memory, CPUs) of future job submissions based on historical use data. ARO can substantially reduce job pending time and improve compute farm utilization by ensuring that jobs are assigned to the best queue/machine combination.
Read the full article on ARO in this issue of Insight.
Learn more about the Lynx Design System.
As part of Synopsys' Optical Design products, CODE V is used for the optimization, analysis, and tolerancing of image-forming optical systems and free-space photonic devices. CODE V version 10.5 features enhancements to improve the accuracy and consistency in tolerancing calculations and also introduces the new Reduce Tolerance Sensitivity control. To read the full set of release notes, log in to your SolvNet account.
Learn more about CODE V.
CATS is a highly scalable and flexible software application that transcribes complex design data into machine readable instructions for e-beam and laser mask writers. Delivering superior slicing quality, uniformity, symmetry, and advanced sliver control, CATS' advanced fracture engine offers unmatched quality. The latest version of CATS (G-2012.09) provides enhancements and improvements to the tool, including increased performance, reduced VSB12 Direct Output file sizes, and enhancements to the DQM job list and description. Synopsys customers can access their SolvNet account to view the full release notes as well as download instructions.
Learn more about CATS.